NDLI: Lattice scheduling and covert channels

Content Provider	IEEE Xplore Digital Library
Author	Hu, W.-M.
Copyright Year	1992
Description	Author affiliation: Digital Equipment Corp., Littleton, MA, USA (Hu, W.-M.)
Abstract	The lattice scheduler is a process scheduler that reduces the performance penalty of certain covert-channel countermeasures by scheduling processes using access class attributes. The lattice scheduler was developed as part of the covert-channel analysis of the VAX security kernel. The VAX security kernel is a virtual-machine monitor security kernel for the VAX architecture designed to meet the requirements of the A1 rating from the US National Computer Security Center. After describing the cache channel, a description is given of how this channel can be exploited using the VAX security kernel as an example. The author discusses how this channel can be closed and the performance effects of closing the channel. The lattice scheduler is introduced, and its use in closing the cache channel is demonstrated. Finally, the work illustrates the operation of the lattice scheduler through an extended example and concludes with a discussion of some variations of the basic scheduling algorithm.
Starting Page	52
Ending Page	61
File Size	761440
Page Count	10
File Format	PDF
ISBN	0818628251
DOI	10.1109/RISP.1992.213271
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lattices Kernel Computer security National security Invasive software Processor scheduling Computerized monitoring Timing Trademarks Computer architecture
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reducing timing channels with fuzzy time

Covert and Side Channels Due to Processor Architecture

Auditing the use of covert storage channels in secure systems

An analysis of covert timing channels

Protection against covert storage and timing channels

A user-level framework for auditing and monitoring

Run-time detection of covert channels

CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware

Formal analysis for real-time scheduling

Lattice scheduling and covert channels

Similar Documents

Reducing timing channels with fuzzy time

Covert and Side Channels Due to Processor Architecture

Auditing the use of covert storage channels in secure systems

An analysis of covert timing channels

Protection against covert storage and timing channels

A user-level framework for auditing and monitoring

Run-time detection of covert channels

CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware

Formal analysis for real-time scheduling

Lattice scheduling and covert channels