NDLI: Dynamic Fault Imaging of VLSI Random Logic Devices

Content Provider	IEEE Xplore Digital Library
Author	May, T.C. Scott, G.L. Meieran, E.S. Winer, P. Rao, V.R.
Copyright Year	1984
Description	Author affiliation: INTEL Corporation, 3065 Bowers Ave., Santa Clara, CA 95051 (May, T.C.; Scott, G.L.; Meieran, E.S.; Winer, P.; Rao, V.R.)
Abstract	A technique is described for acquiring and imaging faults in random logic devices such as microprocessors and other VLSI chips. Logic states for both faulty and fault-free devices are imaged separately by means of stroboscopic voltage contrast in a scanning electron microscope and are then stored as incremental time sequences of images. These sequences represent the time evolution of states during a particular device test and are then compared in an image array processor. The divergences or changes between the faulty and fault-free device evolutions represent faults, which are then displayed on a color monitor. The architecture and implementation of the Dynamic Fault Imager is described. Several examples using highly-integrated microprocessors are given, including the imaging of functional failures, voltage marginalities, and critical speed path mapping. A partial classification of faults is presented, as well as a discussion of future trends. The technique appears to have wide application to solving problems in the design and manufacturing of future VLSI devices.
Starting Page	95
Ending Page	108
File Size	18795734
Page Count	14
File Format	PDF
ISSN	07350791
DOI	10.1109/IRPS.1984.362025
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1984-04-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Logic devices Circuit faults Microprocessors Logic testing Failure analysis Voltage Fault diagnosis EPROM Pins
Content Type	Text
Resource Type	Article

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