NDLI: An algorithm based fault tolerance technique for safety-critical applications

Content Provider	IEEE Xplore Digital Library
Author	Smith, D.T. DeLong, T.A. Johnson, B.W. Profeta III, J.A.
Copyright Year	1997
Description	Author affiliation: Virginia Univ., Charlottesville, VA, USA (Smith, D.T.)
Abstract	The design of safety critical systems is a difficult and time consuming task. The traditional design of safety critical systems involves the use of proprietary hardware and software. The full custom design approach is becoming unacceptable because performing a complete redesign for each different class of control applications is unacceptable. Additionally, traditional safety critical systems are designed based on locating all faults in the system which can affect safety via diagnostics. The increasing complexity of the control algorithms which must be processed in a safety critical fashion makes the fault space of the system increase in size to the point where the design of diagnostics becomes quite difficult and time consuming. One promising methodology which can assist in reducing the design effort associated with safety critical systems while using commercial off-the-shelf (COTS) components is algorithm-based fault tolerance (ABFT). Unfortunately, existing ABFT techniques are currently not suitable for safety critical applications. A new safety critical ABFT (SC-ABFT) technique is presented. The checking scheme for the SC-ABFT method is derived based on verifying the correctness of a given control application as it is being evaluated. Also, the probability of detecting a safety-critical error can made as close to 1.0 as desired by varying certain parameters.
Starting Page	278
Ending Page	285
File Size	1009266
Page Count	8
File Format	PDF
ISBN	0780337832
ISSN	0149144X
DOI	10.1109/RAMS.1997.571720
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-01-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Algorithm design and analysis Switches Fault tolerant systems Software safety Application software Control systems Signal design Hardware Size control
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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