NDLI: A 48 channel pulse shape digitizer with DSP

Content Provider	IEEE Xplore Digital Library
Author	Martin, J.-P. Amaudruz, P.-A.
Copyright Year	2005
Description	Author affiliation: Montreal Univ., Que. (Martin, J.-P.)
Abstract	A 48 channel, 40-65 MS/sec, 10 bit pulse shape digitizer card has been designed in the VME-6U form factor. The design uses 6 octal flash analog to digital converter (FADC) chips (ADS5121 or ADS5122) from Texas Instruments. The FADCs are read out by 6 Altera Cyclone FPGAs. A $7^{th}$ FPGA is used to collect and merge the event fragments. The present firmware includes trigger latency buffers, waveform segment buffers, real-time digital filtering, time stamp generation, amplitude evaluation, event formatting and buffering, plus a simple VME A24D32 interface. The design also includes a source synchronous bi-directional serial LVDS link for the interconnection of the modules to a large system. The first version of the module is designed for an R&D test readout system connected to a few hundred drift chamber cathode pads or TPC cathode/anode pads. The final version is intended for the readout of the KOPIO preradiator cathode drift chamber pads (~75,000 channels). This version only have the LVDS interconnect. The present design using off-the-shelf commercial components is an interesting alternative to an ASIC approach for intermediate size readout system. It occupies about 3 times the area of an equivalent ASIC system, and has comparable power dissipation. In its present form, the development version of the module can be useful as a general purpose waveform digitizer and DSP with its high density (48 channels per single width VME module) at a relatively low cost per channel
File Size	196039
File Format	PDF
ISBN	0780391837
DOI	10.1109/RTC.2005.1547474
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-04
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pulse shaping methods Shape Digital signal processing Cathodes Field programmable gate arrays Application specific integrated circuits Digital signal processing chips Analog-digital conversion Instruments Cyclones
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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