NDLI: Relaxing Mixed-Criticality Scheduling Strictness for Task Sets Scheduled with FP

Content Provider	IEEE Xplore Digital Library
Author	Santy, F. George, L. Thierry, P. Goossens, J.
Copyright Year	2012
Abstract	Current trends in the embedded systems field tend to collocate multiple functionalities upon a single computing platform, the aim being to reduce both the size and cost of embedded systems. Nevertheless, it is unlikely that all functionalities share the same level of criticality, and certification of the system has to be achieved using varying degrees of rigorousness. Typically, a task tau_i is guaranteed to meet its temporal constraints up to a criticality level that is equal to its own criticality. When those conditions are no longer met, i.e. when another higher priority task tau_j has its execution time that exceeds its Worst Case Execution Time (WCET) w.r.t. the criticality level of tau_i, a common approach is to suspend tau_i. However, in some cases, it may not be necessary to suspend tasks with a lower criticality immediately as they could still be executed without compromising the deadlines of high criticality tasks. As a step towards this aim, we propose a method, denoted Latest Completion Time (LCT), that allows lower criticality tasks to proceed with their execution as long as they do not prevent higher criticality tasks from meeting their deadlines. Furthermore, we show that tasks suspension can only be temporary, and prove that a particular definition of idle times can be used to reset the system's criticality level. Finally, we study the performances of our LCT mechanism w.r.t. the classical mechanism that suspends a task as soon as the system criticality level becomes higher than its own criticality.
Starting Page	155
Ending Page	165
File Size	371270
Page Count	11
File Format	PDF
ISBN	9781467320320
ISSN	10683070
DOI	10.1109/ECRTS.2012.39
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-11
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Time factors Context Suspensions Estimation Electronic mail Embedded systems Processor scheduling Fixed Priority Schedulability Mixed-Criticality Allowance Latest Completion Time
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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