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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bril, R.J. Lukkien, J.J. Verhaegh, W.F.J. |
| Copyright Year | 2007 |
| Description | Author affiliation: Tech. Univ. Eindhoven, Eindhoven (Bril, R.J.; Lukkien, J.J.) |
| Abstract | Fixed-priority scheduling with deferred preemption (FPDS) has been proposed in the literature as a viable alternative to fixed-priority preemptive scheduling (FPPS), that both reduces the cost of arbitrary preemptions and removes the need for non-trivial resource access protocols. This paper shows that existing worst-case response time analysis of hard real-time tasks under FPDS, arbitrary phasing and relative deadlines at most equal to periods is both pessimistic and optimistic. This paper provides a revised analysis, resolving the problems with the existing approaches. The analysis assumes a continuous scheduling model. It is shown that the critical instant, longest busy period, and worst-case response time for a task are suprema rather than maxima for all tasks, except for the lowest priority task. Moreover, it is shown that the analysis is not uniform for all tasks, i.e. the analysis for the lowest priority task differs from the analysis of the other tasks, because only the lowest priority task cannot be blocked. To build on earlier work, the worst-case response time analysis for FPDS is expressed in terms of known worst-case analysis results for FPPS. The paper includes pessimistic variants of the analysis, which are uniform for all tasks. |
| Starting Page | 269 |
| Ending Page | 279 |
| File Size | 218590 |
| Page Count | 11 |
| File Format | |
| ISBN | 0769529143 |
| ISSN | 10683070 |
| DOI | 10.1109/ECRTS.2007.38 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-07-04 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay Access protocols Processor scheduling Real time systems Costs Laboratories Cache memory Bridges System performance Degradation |
| Content Type | Text |
| Resource Type | Article |
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