NDLI: Limited Pre-emptive Global Fixed Task Priority

Content Provider	IEEE Xplore Digital Library
Author	Marinho, J. Nelis, V. Petters, S.M. Bertogna, M. Davis, R.I.
Copyright Year	2013
Description	Author affiliation: CISTER, Polytech. Inst. of Porto, Porto, Portugal (Marinho, J.; Nelis, V.; Petters, S.M.) \|\| Univ. of Modena, Modena, Italy (Bertogna, M.) \|\| Univ. of York, York, UK (Davis, R.I.)
Abstract	In this paper a limited pre-emptive global fixed task priority scheduling policy for multiprocessors is presented. This scheduling policy is a generalization of global fully pre-emptive and non-pre-emptive fixed task priority policies for platforms with at least two homogeneous processors. The scheduling protocol devised is such that a job can only be blocked at most once by a body of lower priority non-pre-emptive workload. The presented policy dominates both fully pre-emptive and fully non-pre-emptive with respect to schedulability. A sufficient schedulability test is presented for this policy. Several approaches to estimate the blocking generated by lower priority non-pre-emptive regions are presented. As a last contribution it is experimentally shown that, on the average case, the number of pre-emptions observed in a schedule are drastically reduced in comparison to global fully pre-emptive scheduling.
Sponsorship	IEEE Comput. Soc.
Starting Page	182
Ending Page	191
File Size	276784
Page Count	10
File Format	PDF
ISBN	9781479920068
ISSN	10528725
DOI	10.1109/RTSS.2013.26
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-03
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Processor scheduling Interference Multicore processing Time factors Job shop scheduling Schedules
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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