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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sha, L. Rajkumar, R. Lehoczky, J. |
| Copyright Year | 1990 |
| Description | Author affiliation: Carnegie Mellon Univ., Pittsburgh, PA, USA (Sha, L.) |
| Abstract | A simple but efficient architecture for building multiprocessors is to connect several processors to a common backplane bus. The backplane acts as a shared resource in this architecture and contention for its use by different bus modules must be resolved. In a real-time system, this backplane must also provide scheduling support such that the timing behavior of the resulting system is analyzable. In addition, the support primitives for real-time scheduling on a backplane bus must also be constrained by the economic considerations associated with a bus standard that is intended to support both time sharing and real-time applications. The authors review the design considerations to support real-time systems in the IEEE Futurebus+ backplane specification and describe how this backplane can be used to satisfy timing constraints in priority-driven real-time systems. |
| Starting Page | 331 |
| Ending Page | 340 |
| File Size | 1146710 |
| Page Count | 10 |
| File Format | |
| ISBN | 0818621125 |
| DOI | 10.1109/REAL.1990.128765 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1990-12-05 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Backplanes Real time systems Processor scheduling Job shop scheduling Clocks Synchronization Timing Costs Protocols Logic |
| Content Type | Text |
| Resource Type | Article |
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