NDLI: Integrated time- and event-triggered scheduling - An overhead analysis on the ARM architecture

Content Provider	IEEE Xplore Digital Library
Author	Schorr, S. Fohler, G.
Copyright Year	2013
Description	Author affiliation: Tech. Univ. Kaiserslautern, Kaiserslautern, Germany (Schorr, S.; Fohler, G.)
Abstract	Slot shifting is a method to combine time-triggered and event-triggered scheduling of real-time systems. It analyzes offline constructed scheduling tables for the amount and location of unused resources, called spare capacities, which are used to accommodate event-triggered activities, such as aperiodic tasks. Spare capacities are efficiently represented to indicate available resources and the flexibility to shift offline scheduled tasks while maintaining their feasibility with respect to their original timing constraints. In this paper, we study the overhead costs involved in the practical implementation of slot shifting. We present results from measurements on the cycle accurate multi-processor systems-on-chip simulator MPARM, which indicate the execution time and memory costs of the various steps of online slot shifting for the ARM architecture. These allow a designer to select configurations and trade-offs for the implementation. We present the insights gained which lead to a redesign of the original algorithm.
Sponsorship	IEEE Comput. Soc.
Starting Page	165
Ending Page	174
File Size	796662
Page Count	10
File Format	PDF
ISBN	9781479908509
ISSN	15332306
DOI	10.1109/RTCSA.2013.6732216
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-19
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Schedules Scheduling Algorithm design and analysis Hardware Heuristic algorithms Servers
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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