NDLI: Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems

Content Provider	IEEE Xplore Digital Library
Author	Bak, S. Gang Yao Pellizzoni, R. Caccamo, M.
Copyright Year	2012
Abstract	Real-time scheduling of memory-intensive applications is a particularly difficult challenge. On a multi-core system, not only is the CPU scheduling an issue, but equally important is the management of mutual interference among tasks caused by simultaneous access to the shared main memory. To confront this problem, we explore real-time schedulers for task sets which adhere to the Predictable Execution Model (PREM). In each PREM-compliant task, execution is divided into phases which retrieve data from main memory, and phases which perform local computation using previously-cached data. In this work, we perform a simulation-based analysis with the goal of determining which schedulers are generally better at scheduling PREM-compliant task sets. We investigate several memory intensive real-time benchmarks from the EEMBC benchmark suite, in order to drive our task set generation parameters. We elaborate on a PREM-complaint task set simulator which we designed specifically to be able to simulate PREM-compliant tasks. The overall best scheduling policy we found, which we call M-LAX, schedules access to memory in a no preemptive fashion according to a least-laxity-first policy. M-LAX outperforms an EDF-based approach, a previously-analyzed TDMA arbitration scheme, and the unscheduled case where tasks interfere when accessing memory.
Starting Page	300
Ending Page	309
File Size	692575
Page Count	10
File Format	PDF
ISBN	9781467330176
ISSN	15332306
e-ISBN	9780769548241
DOI	10.1109/RTCSA.2012.48
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-19
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems Benchmark testing Multicore processing Prefetching Processor scheduling Interference Memory management tdma real-time scheduling multicore PREM predictable execution model simulator simulation eembc benchmark scheduling M-LAX least-laxity first
Content Type	Text
Resource Type	Article

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