NDLI: Graphically notated fault modeling and safety analysis in the context of electric and electronic architecture development and functional safety

Content Provider	IEEE Xplore Digital Library
Author	Adler, N. Hillenbrand, M. Muller-Glaser, K.D. Metzker, E. Reichmann, C.
Copyright Year	2012
Description	Author affiliation: FZI Research Center for Information Technology, Germany (Adler, N.; Hillenbrand, M.) \|\| Vector Informatik GmbH, Germany (Metzker, E.; Reichmann, C.) \|\| Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology, Germany (Muller-Glaser, K.D.)
Abstract	Although fault tree analysis is well established in the industry and its application is proposed by the international standard for functional safety for road vehicles — ISO 26262 — it is often time intensive to perform. Tool chains are long, the line of action is not straightforward, annotations in data models are complex and traceability is not self-evident. To overcome these inconveniences, this paper presents an approach for graphically notated failure modeling, based on an integrated data model for electric and electronic architectures and rapidly performing of fault tree analysis during concept phase of system design. We demonstrate the utilization of existing concepts in the domain of electric and electronic architecture modeling to enrich existing architectures with concepts of fault tree analysis. Also, we demonstrate the model-based specification of failure models, their relation to modeling artifacts of electric and electronic architectures and the automated processing of failure expressions without the necessity to leave the development environment for electric and electronic architecture modeling. The presented methodology supports closer links between the development of architectures for safety-critical systems and failure analysis by facilitating traceability between failure and system modeling based on a common data structure and well-established modeling approaches.
Starting Page	36
Ending Page	42
File Size	586341
Page Count	7
File Format	PDF
ISBN	9781467327862
ISSN	21505500
e-ISBN	9781467327893
e-ISBN	9781467327886
DOI	10.1109/RSP.2012.6380688
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-11
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data models Safety Computer architecture Unified modeling language Fault trees Hardware Software
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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