NDLI: An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processing

Content Provider	IEEE Xplore Digital Library
Author	Ali, Z. Arshad, A. Razzaq, U.
Copyright Year	2010
Description	Author affiliation: Irtiqa Technologies, Pakistan (Ali, Z.; Arshad, A.; Razzaq, U.)
Abstract	The design and implementation of a higher order Moving Target Indication (MTI) engine is presented. This is part of a single chip radar signal processor also incorporating the subsequent algorithms. The bottleneck in use of higher order filters for MTI is not an algorithmic one but one related to implementation. Thus the challenge is to minimize area utilization and achieve the required speed. The proposed architecture employs the use of multiple offchip memory banks for achieving the required memory bandwidth and use of dedicated FPGA resources for area minimization. The requirement of stacking a large number of radar returns in memory and then reading them all for filtering within a single return time demands a parallel memory reading and data processing approach. But this demand has to be balanced with the requirement to consume as little area as possible to leave room for the following algorithms. Considering these constraints, a semi parallel architecture employing multiple filters, each built around a DSP48 slice configured as a Multiply Accumulate (MACC) unit in a time shared manner is used. An analysis of various factors that affect speed and area is also made. The architecture is implemented on a Virtex-4SX35 FPGA using Xilinx XtremeDSP Kit. The design is tested using unprocessed baseband data from a TA-10K air traffic control radar. Results show a marked improvement in the clutter suppression capability of the radar. The design achieves the required speed using only 7% of the available FPGA slices. Thus, not only can the other algorithms be implemented on the same chip but there is room for enhancements as well.
Starting Page	1
Ending Page	7
File Size	374843
Page Count	7
File Format	PDF
ISBN	9781424470730
e-ISBN	9781424470747
e-ISBN	9781424470723
DOI	10.1109/RSP.2010.5656326
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Field programmable gate arrays Finite impulse response filter Clocks Memory management Radar
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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