NDLI: Cache configuration exploration on prototyping platforms

Content Provider	IEEE Xplore Digital Library
Author	Chuanjun Zhang Vahid, F.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Riverside, CA, USA (Chuanjun Zhang)
Abstract	We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself can be configured with respect to the total size, associativity, line size, and way prediction. The cache architecture includes an explorer component that efficiently searches the large space of possible configurations for the set of points representing meaningful tradeoffs between performance and energy - the Pareto-optimal set. We provide results of experiments showing that the architecture effectively finds a good set of Pareto points for numerous Powerstone and MediaBench embedded system benchmarks. Our architecture eliminates the need for time-consuming simulations to determine the best cache configuration, and imposes little power overhead and reasonable size overhead.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Design Autom. IEEE Comput. Soc. Tech. Committee on Simulation
Starting Page	164
Ending Page	170
File Size	325122
Page Count	7
File Format	PDF
ISBN	0769519431
ISSN	10746005
DOI	10.1109/IWRSP.2003.1207044
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prototypes Application specific integrated circuits Computer architecture Microprocessors Memory architecture Embedded system Embedded computing Virtual prototyping Testing Computer science
Content Type	Text
Resource Type	Article
Subject	Computer Science

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