NDLI: System prototyping by integration of reconfigurable hardware into a heterogeneous system model

Content Provider	IEEE Xplore Digital Library
Author	Buchenrieder, K. Nageldinger, U. Pyttel, A. Sedlmeier, A.
Copyright Year	2002
Description	Author affiliation: Infineon Technol. AG, Munich, Germany (Buchenrieder, K.; Nageldinger, U.; Pyttel, A.; Sedlmeier, A.)
Abstract	In this paper, we present an efficient methodology to functionally verify high performance algorithms using a Hardware/Software Prototype based on reconfigurable hardware attached to a standard PC We start from a conceptual design on system level using the commercial Cadence Cierto VCC tool, by defining the system in several behavioral blocks, each of them having the functionality described in standard C or C++. This software-only system is then refined by selecting certain blocks to be implemented in hardware, which are then described in Handel-C, then compiled and mapped to Xilinx Virtex FPGAs. The hardware blocks are seamlessly integrated into the VCC environment by stub modules, which perform the hardware/software interfacing and communication via shared memory DMA transfers. This paper presents the methodology and illustrates it using an example of a Viterbi encoder/decoder.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Simulation IEEE Comput. Soc. Tech. Committee on Design Autom
Starting Page	115
Ending Page	121
File Size	391326
Page Count	7
File Format	PDF
ISBN	076951703X
ISSN	10746005
DOI	10.1109/IWRSP.2002.1029746
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-07-01
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prototypes Hardware Software prototyping Software performance Software standards Software algorithms Software tools Algorithm design and analysis Field programmable gate arrays Viterbi algorithm
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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