NDLI: Rapid prototyping for hardware accelerated elliptic curve public-key cryptosystems

Content Provider	IEEE Xplore Digital Library
Author	Ernst, M. Klupsch, S. Hauck, O. Huss, S.A.
Copyright Year	2001
Description	Author affiliation: Integrated Circuits & Syst. Lab., Darmstadt Univ. of Technol., Germany (Ernst, M.)
Abstract	A generator-based design and validation methodology for rapid prototyping of elliptic curve public-key cryptosystem hardware is described. By their very nature, cryptosystems challenge both design and validation. Pure RTL-based synthesis is as unsuitable as high-level synthesis. Instead, a generator program accepts the two main parameters - the key size and the multiplier radix - and creates a highly efficient custom RTL description which is synthesized into a FPGA. This approach benefits the design in that it allows one to effortlessly exploit the available resources on the FPGA for variable requirements of security and performance. It is also advantageous for validation of the correctness of the design as, for small parameter values, the design can be tested exhaustively. Thus, the correctness for large key sizes depends only on the correctness of the generator. Furthermore, deploying FPGAs supports integration of an ASIC realisation of the same algorithm, which boosts performance. By emulating its interface, the ASIC can be accommodated even before fabrication, thus enabling mixed FPGA/ASIC acceleration of elliptic curve cryptosystems.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Design Autom.
Starting Page	24
Ending Page	29
File Size	669864
Page Count	6
File Format	PDF
ISBN	0769512062
DOI	10.1109/IWRSP.2001.933834
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prototypes Hardware Acceleration Elliptic curves Field programmable gate arrays Application specific integrated circuits Elliptic curve cryptography Design methodology Public key cryptography High level synthesis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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