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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Krupnova, H. Dinh Duc Anh Vu Saucier, G. Boubal, M. |
| Copyright Year | 1998 |
| Description | Author affiliation: Inst. Nat. Polytech. de Grenoble, France (Krupnova, H.) |
| Abstract | The paper presents a strategy for high-speed prototyping on FPGAs. The traditional "glue" synthesis strategy may not be sufficient for obtaining FPGA prototypes working at real speed. A key possibility to accelerate the performance of FPGA designs is the utilisation of the architectural features of modern FPGAs. To do this, no "push-button" solutions exists. The way to do this is to process one by one the critical blocks of the design and to decide about the implementation strategy for each block. As an example, a case study of a microprocessor circuit is presented. The microprocessor should be able to work in real time at 10 MHz frequency. To reach this speed in the Altera FLEX 10 KA technology, a special implementation strategy was elaborated for the microprocessor's RAM and ALU blocks. |
| Starting Page | 13 |
| Ending Page | 18 |
| File Size | 92444 |
| Page Count | 6 |
| File Format | |
| ISBN | 0818684798 |
| ISSN | 10746005 |
| DOI | 10.1109/IWRSP.1998.676662 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-06-05 |
| Publisher Place | Belgium |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Prototypes Computer aided software engineering Field programmable gate arrays Microprocessors Read-write memory Application specific integrated circuits Random access memory Acceleration Memory architecture Logic |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Science |
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