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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chao-Ching Hung Ding-Shiuan Shen Shen-Iuan Liu |
| Copyright Year | 2008 |
| Description | Author affiliation: Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei (Chao-Ching Hung; Ding-Shiuan Shen; Shen-Iuan Liu) |
| Abstract | A 40 GHz fractional-N frequency synthesizer with a divide-by-64/64.5/65/65.5 fractional multi-modulus divider (MMD) is presented. A second-order 24-bit delta-sigma modulator is used to modulate the fractional MMD. This fractional MMD provides a half division step of a conventional integer MMD. Therefore, a better frequency resolution can be obtained. This frequency synthesizer has been fabricated in a 0.13 um CMOS process. The measured fractional spur is below -50dB. The measured phase noise is -75.3 dBc/Hz and -93.24 dBc/Hz at 1MHz and 3 MHz offset, respectively. The die area is 1.34 x 1.26 $mm^{2}$ and the power dissipation is 105 mW from the supply of 1.5 V. |
| Starting Page | 295 |
| Ending Page | 298 |
| File Size | 574283 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424418084 |
| ISSN | 15292517 |
| DOI | 10.1109/RFIC.2008.4561439 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-06-17 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Frequency synthesizers Voltage-controlled oscillators Delta modulation Circuits Frequency conversion Phase frequency detector Phase noise Power dissipation Transceivers Degradation |
| Content Type | Text |
| Resource Type | Article |
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