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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Muzhou Shao |
| Copyright Year | 2008 |
| Description | Author affiliation: Synopsys Inc., Mountain View (Muzhou Shao) |
| Abstract | As the IC feature size advances to nanometer, IR drop and power network noise produce significant effects on delay and signal integrity. Traditional timing analysis and closure should not be regarded as complete without taking into consideration voltage fluctuation on the PG network. Moreover, the interaction between the timing and IR drop makes this issue more complicated. At the gate level, timing and PG rail analysis need to perform several iterative loops until they come to converge. Whenever the supply voltage changes, the conventional approach of moment-based timing calculation needs to fully re-compute from scratch. However, the variation of the power supply does not affect signal nets and mainly changes the gate driving ability. Based on this observation, we propose a new method to efficiently calculate timing. This method can update timing from arithmetic operations based on results in the previous iteration rather than the time-consuming tree traversal. |
| Starting Page | 301 |
| Ending Page | 304 |
| File Size | 326690 |
| Page Count | 4 |
| File Format | |
| ISBN | 9780769531175 |
| DOI | 10.1109/ISQED.2008.4479744 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-03-17 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Timing Voltage fluctuations Performance analysis Power supplies Rails Integrated circuit noise Delay effects Degradation Signal design Arithmetic |
| Content Type | Text |
| Resource Type | Article |
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