NDLI: A power-aware GALS architecture for real-time algorithm-specific tasks

Content Provider	IEEE Xplore Digital Library
Author	Datta, A. Bhunia, S. Banerjee, N. Roy, K.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Datta, A.; Bhunia, S.; Banerjee, N.; Roy, K.)
Abstract	We propose an adaptive scalable architecture suitable for performing real-time algorithm-specific tasks. The architecture is based on the globally asynchronous and locally synchronous (GALS) design paradigm. We demonstrate that for different real-time commercial applications with algorithm-specific jobs like online transaction processing, Fourier transform etc., the proposed architecture allows dynamic load-balancing and adaptive inter-task voltage scaling. The architecture can also detect process-shifts for the individual processing units and determine their appropriate operating conditions. Simulation results for two representative applications show that for a random job distribution, we obtain up to 67% improvement in MOPS/W (millions of operations per second per watt) over a fully synchronous implementation.
Sponsorship	IEEE Electron Device Soc. (EDS) IEEE Components, Packaging & Manuf. Technol. Soc. (CPMT)
Starting Page	358
Ending Page	363
File Size	216301
Page Count	6
File Format	PDF
ISBN	0769523013
DOI	10.1109/ISQED.2005.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Frequency Dynamic voltage scaling Computer architecture Degradation Delay Application software Fourier transforms Limiting Batteries
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

1A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks∗

Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC

Feedback-based dynamic voltage and frequency scaling for memory-bound real-time applications

Frequency-aware energy optimization for real-time periodic and aperiodic tasks

An integrated approach for applying dynamic voltage scaling to hard real-time systems

Frequency-aware energy optimization for real-time periodic and aperiodic tasks

Time-efficient power-aware scheduling for periodic real-time tasks

Coexistence of Real-Time and Interactive & Batch Tasks in DVS Systems

Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems

A power-aware GALS architecture for real-time algorithm-specific tasks

Similar Documents

1A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks∗

Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC

Feedback-based dynamic voltage and frequency scaling for memory-bound real-time applications

Frequency-aware energy optimization for real-time periodic and aperiodic tasks

An integrated approach for applying dynamic voltage scaling to hard real-time systems

Frequency-aware energy optimization for real-time periodic and aperiodic tasks

Time-efficient power-aware scheduling for periodic real-time tasks

Coexistence of Real-Time and Interactive & Batch Tasks in DVS Systems

Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems

A power-aware GALS architecture for real-time algorithm-specific tasks