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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Alexander, J.A. Corley, J.P. Johnson, D.L. Denison, G.J. Hodge, K. Pankuch, P. Ramirez, J.J. |
| Copyright Year | 1989 |
| Description | Author affiliation: Sandia National Laboratories (Alexander, J.A.) |
| Abstract | Hermes III is a new 20-MV, 730-kA, 40-ns pulsed power accelerator. In Hermes III, eighty pulse forming lines (PFLs) generate 1.1-MV, 220-kA pulses, which are then added in a series/parallel configuration to produce the desired output pulse. Under normal Hermes-III operation, the PFLs produce a /spl tilde/40-ns FWHM pulse with a /spl tilde/15-ns, 10-90% rise time, and a one-sigma jitter of /spl tilde/4 ns. The Hermes-III water-dielectric PFLs have undergone 18 months of testing. During this period, over 59,000 PFL-shots have been accumulated, most of these at or near peak power. The PFLs have met design specifications, and they have proven to be highly reliable. This paper presents a brief overview of the PFL design, together with a detailed discussion of the system performance and limitations during this extensive testing period. A modification to the PFLs to produce a ramped output pulse was designed and tested. Results indicate that a ramped output pulse can be produced using a stepped impedance PFL. |
| Starting Page | 575 |
| Ending Page | 578 |
| File Size | 550775 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/PPC.1989.767551 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-06-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Switches Conductors Transmission lines Testing Voltage Space vector pulse width modulation Laboratories Impedance Water storage Capacitors |
| Content Type | Text |
| Resource Type | Article |
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