NDLI: High threshold voltage p-GaN gate power devices on 200 mm Si

Content Provider	IEEE Xplore Digital Library
Author	Jongseob Kim Sun-Kyu Hwang Injun Hwang Hyoji Choi Soogine Chong Hyun-Sik Choi Woochul Jeon Hyuk Soon Choi Jun Yong Kim Young Hwan Park Kyung Yeon Kim Jong-Bong Park Jong-Bong Ha Ki Yeol Park Jaejoon Oh Jai Kwang Shin U-In Chung In-Kyeong Yoo Kinam Kim
Copyright Year	2013
Description	Author affiliation: Samsung Adv. Inst. of Technol., Samsung Electron. Co., Ltd., Yongin, South Korea (Jongseob Kim; Sun-Kyu Hwang; Injun Hwang; Hyoji Choi; Soogine Chong; Hyun-Sik Choi; Woochul Jeon; Hyuk Soon Choi; Jun Yong Kim; Young Hwan Park; Kyung Yeon Kim; Jong-Bong Park; Jong-Bong Ha; Ki Yeol Park; Jaejoon Oh; Jai Kwang Shin; U-In Chung; In-Kyeong Yoo; Kinam Kim)
Abstract	In this paper, we present high threshold voltage, low on-resistance, and high speed GaN-HEMT devices using a p-GaN layer in the gate stack. There are three novel features - first, for the first time, p-GaN gate HEMTs were fabricated on a 200-mm GaN on Si substrate using a Au-free fully CMOS-compatible process. Second, good electrical characteristics, including a threshold voltage of higher than 2.8 V, a low gate leakage current, no hysteresis, and fast switching, were obtained by employing a p-GaN and W gate stack. Finally, TO-220 packaged p-GaN gate HEMT devices, which can sustain a gate bias of up to 20 V, were demonstrated. Such properties indicate that our p-GaN HEMT devices are compatible with the conventional gate drivers for Si power devices.
Starting Page	315
Ending Page	318
File Size	1252062
Page Count	4
File Format	PDF
ISBN	9781467351348
ISSN	1943653X
e-ISBN	9781467351362
DOI	10.1109/ISPSD.2013.6694412
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-26
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates HEMTs MODFETs Gallium nitride Silicon Switches Current measurement
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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