NDLI: Cryogenic operation of 4H-SiC Schottky rectifiers

Please wait, while we are loading the content...

2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

2012 24th International Symposium on Power Semiconductor Devices and ICs

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs

2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD)

2009 21st International Symposium on Power Semiconductor Devices & IC's

2008 20th International Symposium on Power Semiconductor Devices and IC's

Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's

2006 IEEE International Symposium on Power Semiconductor Devices and IC's

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs

ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings.

Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics

Proceedings of the 14th International Symposium on Power Semiconductor Devices and ICs (Cat. No.02CH37306)

Safe operating area - a new frontier in Ldmos design

Modern applications of power electronics to marine propulsion systems

Review of compound semiconductor devices for RF power applications

Low on-resistance and low feedback-charge, lateral power MOSFETs with multi-drain regions for high-efficient DC/DC converters

Fully self-aligned power trench-MOSFET utilising 1 /spl mu/m pitch and 0.2 /spl mu/m trench width

Ultra low on-resistance SBD with p-buried floating layer

Dual gate lateral inversion layer emitter transistor

Extending the boundary limits of high voltage IGBTs and diodes to above 8 kV

10 kV power semiconductors - breakthrough for 6.9 kV medium voltage drives

New collector design concept for 4.5 kV injection enhanced gate transistor (IEGT)

Hybrid all-SiC MOS-gated bipolar transistor (MGT)

4H-SiC npn bipolar junction transistors with BV/sub CEO/ > 3,200 V

5 kV 4H-SiC SEJFET with low RonS of 69m/spl Omega/cm/sup 2/

27 m/spl Omega/-cm/sup 2/, 1.6 kV power DiMOSFETs in 4H-SiC

Robust, 1000 V, 130 m/spl Omega/-cm/sup 2/, lateral, two-zone RESURF MOSFETs in 6H-SiC

Thin-layer silicon-on-insulator high-voltage PMOS device and application

Extended (180 V) voltage in 0.6 /spl mu/m thin-layer-SOI A-BCD3 technology on 1 /spl mu/m BOX for display, automotive and consumer applications

Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST)

A high performance complementary bipolar process using PBSOI technique

10 kV IGBT press pack modules with series connected chips

120 V BiC-DMOS process for the latest automotive and display applications

120 V multi RESURF junction barrier Schottky rectifier (MR-JBS)

150-V class superjunction power LDMOS transistor switch on SOI

1700 V-IGBT3: field stop technology with optimized trench structure $trend setting for the high power applications in industry and traction

750 A, 75 V MOSFET power module with sub-nH inductance

A new lateral conductivity modulated thyristor with current saturation and low turn-off time

A thin-layer high-voltage silicon-on-insulator hybrid LDMOS/LIGBT device

Conductivity modulation improvement in 6.5 kV trench UMOS insulated gate bipolar transistors

Correlation between static and dynamic SOA (energy capability) of RESURF LDMOS devices in smart power technologies

Cryogenic operation of 4H-SiC Schottky rectifiers

Defect-less trench filling of epitaxial Si growth by H/sub 2/ annealing

Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance

Double-side IGBT phase leg architecture for reduced recovery current and turn-on loss

Dynamics of maximum junction temperature of power MOSFETs

Growth and reliability of thick gate oxide in U-trench for power MOSFETs

Highly reliable LDMOSFETs employing uneven racetrack sources for PDP driver applications

High-voltage UMOSFETs in 4H SiC

IGBT driver chipset for high power applications

Investigations on the stability of dynamic avalanche in IGBTs

New SiGe power bipolar transistors with the optimum base and emitter structures

Non thermal destruction mechanisms of IGBTs in short circuit operation

Switching performance of low-voltage N-channel trench MOSFETs

Optimization of IGBT in power factor correction module for home appliance

Robust 80 V LDMOS and 100 V DECMOS in a streamlined SOI technology for analog power applications

Switching properties of 2 kV SiC-SIT

The concave junction: an attractive topology to design specific junction terminations

The MOS controlled super junction transistor (SJBT): a new, highly efficient, high power semiconductor device for medium to high voltage applications

Tunable oxide-bypassed VDMOS (OBVDMOS): breaking the silicon limit for the second generation

Ultra high frequency oscillations in the reverse recovery current of fast diodes

Very low R/sub ON/ measured on 4H-SiC accu-MOSFET high power device

A 3V to 6V in, 6A out synchronous buck PWM integrated FET switcher design uses state-of-art power IC technology

Design of a 4 MHz, 5V to 1V monolithic voltage regulator chip

Power performance optimization of a new smart power IC technology targeted for 42V automotive electrical system and high-power applications

I3T80: a 0.35 /spl mu/m based system-on-chip technology for 42 V battery automotive applications

A comparison of electron, proton and helium ion irradiation for the optimization of the CoolMOS/spl trade/ body diode

Break-through of the Si limit under 300 V breakdown voltage with new concept power device: super 3D MOSFET

Manufacturing of high aspect-ratio p-n junctions using vapor phase doping for application in multi-Resurf devices

24 m/spl Omega/cm/sup 2/ 680 V silicon superjunction MOSFET

3 kV 600 A 4H-SiC high temperature diode module

Reliability of pressure contacted intelligent integrated power modules

Guard ring assisted RESURF: a new termination structure providing stable and high breakdown voltage for SiC power devices

A new junction termination technique using ICP RIE for ideal breakdown voltages

Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA

Drain profile engineering of RESURF LDMOS devices for ESD ruggedness

Analytical model for thermal instability of low voltage power MOS and SOA in pulse operation

Active pull-down protection for full substrate current isolation in smart power IC's

Advanced wide cell pitch CSTBTs having light punch-through (LPT) structures

Investigation on the short-circuit capability of 1200 V trench gate field-stop IGBTs

Ultra high switching speed 600 V thin wafer PT-IGBT based on new turn-off mechanism

Enhanced IGBT self clamped inductive switching (SCIS) capability through vertical doping profile and cell optimization

Analysis of LDMOS structure with inclined p-bottom region

A 30 V class extremely low on-resistance meshed trench lateral power MOSFET

Lateral 10-15 V DMOST with very low 6 mohm.mm/sup 2/ on-resistance

Integration of multi-voltage analog and power devices in a 0.25/spl mu/m CMOS + flash memory process

Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216)

12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)

11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)

Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212)

Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings

Proceedings of International Symposium on Power Semiconductor Devices and IC's: ISPSD '95

Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics

[1993] Proceedings of the 5th International Symposium on Power Semiconductor Devices and ICs

Proceedings of the 4th International Symposium on Power Semiconductor Devices and Ics

[1991] Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs

Proceedings of the 2nd International Symposium on Power Semiconductor Devices and Ics. ISPSD '90.

Cryogenic operation of 4H-SiC Schottky rectifiers

Content Provider	IEEE Xplore Digital Library
Author	Shanbhag, M. Chow, T.P.
Copyright Year	2002
Description	Author affiliation: Center for Power Electron. Syst., Rensselaer Polytech. Inst., Troy, NY, USA (Shanbhag, M.; Chow, T.P.)
Abstract	We report the performance of commercial 4H-SiC Schottky rectifiers at cryogenic temperatures for the first time. The Infineon rectifiers rated 300 V and 600 V have been tested for both forward conduction and reverse blocking at temperatures down to 77 K. The barrier height decreased with temperature while the ideality factor is greater than unity implying that diffusion also plays a role in current conduction at cryogenic temperatures. A two barrier height Schottky effect has been noticed at lower temperatures indicating barrier inhomogeneities in the Schottky contacts. At lower temperatures, tunneling current played a major role in the transport process.
Sponsorship	IEEE Electron Devices Soc. Inst. Electr. Eng. Japan
Starting Page	129
Ending Page	132
File Size	306204
Page Count	4
File Format	PDF
ISBN	0780373189
DOI	10.1109/ISPSD.2002.1016188
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryogenics Rectifiers Temperature Power electronics Voltage Silicon carbide Thyristors Tunneling Switches Circuits
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in