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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tomasevic, M. Milutinovic, V. |
| Copyright Year | 1992 |
| Description | Author affiliation: Dept. of Comput. Eng., Pupin Inst., Belgrade, Yugoslavia (Tomasevic, M.) |
| Abstract | Snoopy protocols represent a very popular class of hardware cache coherence solutions, especially suitable for bus-based, shared memory multiprocessors. It is not firmly established which of the two main approaches (write-invalidate or write-broadcast) is superior over the wide range of applications. An enhancement of write-invalidate protocols is proposed, introducing the word invalidation capability. Simulations with a synthetic workload model were performed, in order to analyze its behavior, and to compare it with the best representatives of write-invalidate and write-broadcast protocols. Performance evaluation was done for simulated workloads with a lower and a higher degree of sharing, as well. An attempt is made to model some effects of process switching and migration. Finally, some implications of using a more advanced bus technology on snoopy protocols performance is discussed. |
| Starting Page | 427 |
| Ending Page | 436 |
| File Size | 852954 |
| Page Count | 10 |
| File Format | |
| ISBN | 0818624205 |
| DOI | 10.1109/HICSS.1992.183192 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1992-01-07 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Protocols Hardware Very large scale integration Broadcasting Computational modeling Coherence Costs Throughput Programming profession Program processors |
| Content Type | Text |
| Resource Type | Article |
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