NDLI: Performance analysis of re-configurable partitioned TLBs

Content Provider	IEEE Xplore Digital Library
Author	Channon, D. Koch, D.
Copyright Year	1997
Description	Author affiliation: Dept. of Comput. Sci. & Software Eng., Newcastle Univ., NSW, Australia (Channon, D.)
Abstract	Conventional address translation mechanisms generally use a translation lookaside buffer (TLB) cache of current page translations to provide virtual-to-physical page addressing. This translation cache is generally shared amongst all processes and between reference types, irrespective of whether they relate to instruction or data references. In this paper, we introduce a reconfigurable partitioned TLB which improves TLB performance by removing cache conflict misses between the distinct reference types. Extensive simulations using selected SPEC95 workloads show that data-reference translations unfairly compete with instruction-reference translations by dominating a standard shared TLB. We compare the traditional shared TLB with both fixed partition and reconfigurable fixed partition TLB structures that segregate instruction and data page translation entries. We show that the partitioned TLB operates optimally when the miss ratio of the instruction-reference partition is maintained at a lower level than that for the data-reference partition. By dynamically preserving the balance between the translation performance of the instruction and data components, a protected "working set" of instruction translation entries can be maintained. This can be achieved within the one TLB structure, with soft partitions separating reference types.
Starting Page	168
Ending Page	177
File Size	1081786
Page Count	10
File Format	PDF
ISBN	0818677430
ISSN	10603425
DOI	10.1109/HICSS.1997.663172
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-01-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance analysis Costs Software systems Computer science Software engineering Protection Computer architecture Partitioning algorithms Central Processing Unit Memory management
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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