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Content Provider | IEEE Xplore Digital Library |
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Author | Donzellini, G. Nervi, S. Ponta, D. Rossi, S. Rovetta, S. |
Copyright Year | 1998 |
Description | Author affiliation: Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy (Donzellini, G.) |
Abstract | This paper presents preliminary results on the design of an Object Coprocessor (OCP) cooperating with a RISC-architecture processor (ARM7, by Advanced RISC Machines Ltd). This coprocessor implements in hardware some low-level processing and control steps required by the object-oriented model. The processor and the OCP constitute a processing architecture whose extended instruction set features "object" treatment capabilities. Some special coprocessor instruction codes ("Object Instructions") have been introduced. Concepts such as "Polymorphism" and "Virtual methods" are supported at the hardware level. Preliminary results using typical object-oriented sequences show a gain in speed over a pure software implementation, on the same RISC machine. The specific design presented here refers to a prototype implementation that is currently under development and supported by the European Union Esprit Project (7517 SUMIS). |
Starting Page | 243 |
Ending Page | 252 |
File Size | 96936 |
Page Count | 10 |
File Format | |
ISBN | 0818682558 |
DOI | 10.1109/HICSS.1998.656272 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1998-01-09 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Coprocessors Hardware Reduced instruction set computing Automatic control Object oriented programming Availability Circuits Process control Object oriented modeling Application software |
Content Type | Text |
Resource Type | Article |
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