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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sandberg, A. Eklöv, D. Hagersten, E. |
| Copyright Year | 2010 |
| Abstract | Contention for shared cache resources has been recognized as a major bottleneck for multicores--especially for mixed workloads of independent applications. While most modern processors implement instructions to manage caches, these instructions are largely unused due to a lack of understanding of how to best leverage them. This paper introduces a classification of applications into four cache usage categories. We discuss how applications from different categories affect each other's performance indirectly through cache sharing and devise a scheme to optimize such sharing. We also propose a low-overhead method to automatically find the best per-instruction cache management policy. We demonstrate how the indirect cache-sharing effects of mixed workloads can be tamed by automatically altering some instructions to better manage cache resources. Practical experiments demonstrate that our software-only method can improve application performance up to 35% on x86 multicore hardware. |
| Starting Page | 1 |
| Ending Page | 11 |
| File Size | 243364 |
| Page Count | 11 |
| File Format | |
| ISBN | 9781424475575 |
| e-ISBN | 9781424475599 |
| e-ISBN | 9781424475582 |
| DOI | 10.1109/SC.2010.44 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Multicore processing Prefetching Data structures Bandwidth |
| Content Type | Text |
| Resource Type | Article |
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