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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Rivera, G. Chau-Wen Tseng |
| Copyright Year | 2000 |
| Description | Author affiliation: University of Maryland (Rivera, G.) |
| Abstract | Compiler transformations can significantly improve data locality for many scientific programs. In this paper, we show iterative solvers for partial differential equations (PDEs) in three dimensions require new compiler optimizations not needed for 2D codes, since reuse along the third dimension cannot fit in cachefor larger problem sizes. Tiling is a program transformation compilers can apply to capture this reuse, but successful application of tiling requires selection of non-conflicting tiles and/or padding array dimensions to eliminate conflicts. We present new algorithms and cost models for selecting tiling shapes and array pads. We explain why tiling is rarely needed for 2D PDE solvers, but can be helpful for 3D stencil codes. Experimental results show tiling 3D codes can reduce miss rates and achieve performance improvements of 17-121% for key scientific kernels, including a 27% average improvement for the key computational loop nest in the SPEC/NAS benchmark MGRID. |
| Starting Page | 32 |
| Ending Page | 32 |
| File Size | 362123 |
| Page Count | 1 |
| File Format | |
| ISBN | 0780398025 |
| ISSN | 10639535 |
| DOI | 10.1109/SC.2000.10015 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-11-04 |
| Access Restriction | Subscribed |
| Rights Holder | Non IEEE |
| Subject Keyword | Jacobian matrices Program processors Kernel Partial differential equations Microprocessors Computer science Educational institutions Optimizing compilers Tiles Costs |
| Content Type | Text |
| Resource Type | Article |
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