NDLI: A parallel bus architecture for artificial neural networks

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A parallel bus architecture for artificial neural networks

Content Provider	IEEE Xplore Digital Library
Author	Cantrell, C. Wurtz, L.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA (Cantrell, C.)
Abstract	A new design for a bus architecture for stochastic artifical networks is discussed. A recent VLSI implementation connects many neurons by broadcasting each neuron's address and activation level in turn for all other neurons to process. Such a scheme requires N steps to completely connect N neurons. The proposed architecture uses stochastic activation levels. Since these outputs are simpler, there is room on the global bus for several neurons to fire in parallel. Each neuron processes all outputs in a set of neurons at once, reducing the number of addressing steps on the bus as well as the actual size of the neuron addressing field. This neuron grouping is especially applicable to backpropagation networks. A simulator for the architecture was written and tested.
File Size	513160
File Format	PDF
ISBN	0780312570
DOI	10.1109/SECON.1993.465674
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-04-04
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Artificial neural networks Neurons Computer simulation Computer networks Face recognition Integrated circuit interconnections Stochastic processes Very large scale integration Broadcasting Computational modeling
Content Type	Text
Resource Type	Article

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