NDLI: Low frequency noise in strained silicon nanowire array MOSFETs and Tunnel-FETs

Content Provider	IEEE Xplore Digital Library
Author	Richter, S. Vitusevich, S. Pud, S. Li, J. Knoll, L. Trellenkamp, S. Schafer, A. Lenk, S. Zhao, Q.T. Offenhausser, A. Mantl, S. Bourdelle, K.K.
Copyright Year	2013
Description	Author affiliation: Peter-Grunberg-Inst., Forschungszentrum Julich, Julich, Germany (Richter, S.; Vitusevich, S.; Pud, S.; Li, J.; Knoll, L.; Trellenkamp, S.; Schafer, A.; Lenk, S.; Zhao, Q.T.; Offenhausser, A.; Mantl, S.) \|\| SOITEC Parc Technol. des Fontaines, Bernin, France (Bourdelle, K.K.)
Abstract	MOSFETs and Tunnel-FETs (TFETs) based on arrays of nanowires (NWs) with 10 × 10 $nm^{2}$ cross-section have been fabricated with strained silicon on insulator substrates. MOSFET devices show near ideal subthreshold slope close to 60 mV/dec proving excellent channel control achieved by high-k/metal gate stack. As expected fundamental differences between MOSFETs and TFETs in current-voltage characteristics are observed and analyzed. Low frequency noise spectra are studied for both types of devices. The devices show different behavior in terms of noise spectral density as a function of the applied gate voltage. A Hooge parameter of α = 7.3 × $10^{-3}$ is derived for the NW MOSFETs.
Starting Page	256
Ending Page	259
File Size	1200838
Page Count	4
File Format	PDF
ISBN	9781479906499
DOI	10.1109/ESSDERC.2013.6818867
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-16
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET Noise Silicon Logic gates Arrays Current measurement MOSFET circuits
Content Type	Text
Resource Type	Article

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