NDLI: 0.25 μmCMOS with $N_{2}O$ nitrided gate oxides

Please wait, while we are loading the content...

2015 45th European Solid State Device Research Conference (ESSDERC)

2014 44th European Solid State Device Research Conference (ESSDERC)

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2010 Proceedings of the European Solid State Device Research Conference

2009 Proceedings of the European Solid State Device Research Conference

ESSDERC 2008 - 38th European Solid-State Device Research Conference

ESSDERC 2007 - 37th European Solid State Device Research Conference

2006 European Solid-State Device Research Conference

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.

32nd European Solid-State Device Research Conference

31st European Solid-State Device Research Conference

30th European Solid-State Device Research Conference

29th European Solid-State Device Research Conference

28th European Solid-State Device Research Conference

27th European Solid-State Device Research Conference

ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference

ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference

ESSDERC '94: 24th European Solid State Device Research Conference

ESSDERC '93: 23rd European solid State Device Research Conference

Proceedings of the 23rd European Solid State Device Research Conference

Supporting organisations

Technical contents

Physics and Technology for MOSFETs at 0.1 micron and Below

Photonic Integrated Circuits

Can cellular automata methods compete with Monte Carlo semiconductor device simulations?

An analytical model of current-splitting in CMOS-compatible lateral bipolar transistors

Analysis and modeling of small-geometry effects on maximum cutoff frequency f and forward transit time in high-speed self-aligned bipolar transistors

Low frequency noise in partially depleted SOI twin-MOSFET's

Random Telegraph Signal related low-frequency noise peaks in submicrometer Si MOST's

Noise Performance of MESFETs and MODFETs: Influence of the Gate Leakage Current

Low-Frequency Noise and Microwave Noise Parameters in Si/SiGe Heterojunction Bipolar Transistors

Polysilicon Thin Film Transistor : a Study of some Techniques of Realisation of the Channel Region and of the Gate

Analysis of Hot Carrier Induced Degradation in Polycrystalline Silicon Thin Film Transistors

Large Area Deposition of Device Quality SiO for Poly Si TFT Fabrication

On the Way to the Silicon Carbide IMPATT

The Role of TCAD in Parasitic Analysis of ICs

Mechanisms of Hot-Carrier Degradation of Analog Device Parameters in n-MOSFETs

Study of process-induced mechanical stresses in multi-chip modules packaged with a chip-on-board technology

Efficient Calculation of 3-D Stress Distributions in Silicon around Embedded Structures

Generation of MOS Model Parameters Covering Statistical Process Variations

Analysis and Modeling of Low Frequency Noise in Extremely Deep Submicron Silicon CMOS Devices

Low-Frequency Noise Sources in Polysilicon Emiter Bipolar Transistors: Influence of Hot-Electron-Induced Degradation and Post-Stress Recovery

Low-Frequency Noise in SOI MOSFETs from Room to Liquid Helium Temperature: Experimental and Numerical Simulation Results

The microscopic interpretation of electron noise in Schottky-barrier diodes

Universal Electrical Characteristics and Frequency Limits of the Permeable Base Transistor

Permeable Base Transistors with Schottky and junction Gates

Optimization of submicron microwave transistors by lateral scaling

Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage

Physical Modelling of Dopant Diffusion: A Key Point for Deep Submicron CMOS Process Simulation

Stress-dependent Oxidation Simulations for Submicron Technologies

2D Numerical Simulation of Titanium Silicide Growth

A model for fast oxide thickness and surface concentration extraction for tunnel oxide capacitors

High Concentration Boron Diffusion Study Using A Complete Point Defect And Dynamic Nucleation Model

Two-Dimensional Modelling of SILO Isolation Structures

Sensitivity of PNP Doping Profiles to Annealing Conditions - Role of Dynamic Clustering Phenomena

Technologies for System Integration: Constraints and Solutions in Modular Process Development

The Design, Fabrication and Characterization of 0.15 μm MOS Devices

Silicon based MIS devices with organic molecular monolayer as ultra-thin insulating film

Identification of thermal and electrical time constants in SOIMOSFETS from small signal measurements

Physical Properties of Silicon CMOS Devices Operated between Liquid Helium and Room Temperature

Process and Design Considerations for Latch-Up Optimization on Deep Sub-Micron CMOS Technology

Selective Epitaxial Bipolar Technology for 25 to 40 Gb/s ICs

Physical identification of an excess base current component in silicided half-micrometer polysilicon-emitter bipolar transistors

Optimisation of BF implanted pnp polysilicon emitter bipolar transistors using rapid thermal annealing

P mono-/p polysilicon layer: Separation of influences on electron transport and their processing dependences

ABCMOS3: A High Precision, High Speed, Modular BiCMOS Process for Analog/Digital Applications

High Current Properties of Combined Schottky/pn Diodes; Interaction between Closely Located Schottky and pn Diodes

The New Limits of Optical Lithography

Design Aspects for Multilayer Interconnections on ICs

The Future of High Density Packaging

Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS

A 0.25μm Fully Planarized CMOS Technology

Optimised Drain/Source Engineering for 0.35 μm NMOS Transistors

Optimisation of a self-aligned twin well without channel stop implant for improved isolation of a 0.4μm CMOS process

Strained Layer Quantum Well Lasers for Optical Communications

Investigation of the Temperature Dependence of Threshold Current Density of GaInP/AlGaInP Multi Quantum Well Lasers

Experimental Analysis of Laser Diode Thermal Characteristics by Voltage Transient Measurements

Carrier Heating induced Picosecond Operation of GaInAsP/InP Laser Diode

High Power Oscillation of Reduced Spatial Hole Burning DFB Laser

Si Heterojunction Bipolar Transistors: the future of silicon bipolar technology or not?

Influence of the Base/Collector-Heterojunction on the Large and Small Signal Behaviour of Si/SiGe-HBTs and Consequences for Applications in High-Speed ICs

Influence of the Ge fraction and distribution in the base of Si/SiGe-HBTs on the transit frequency

On the electron minority carrier mobility and the effective bandgap in heterojunction bipolar transistors with strained Si-base

Reactive Ion Etching Damage to Strained Si Heterojunction Diodes

Physical Modelling and Simulation of Advanced Si-devices - An Industrial Approach

Modelling of Anomalous Boron Diffusion in Si/SiHBTs

Current Filamentation and Thermal Instability in a Power BJT Array Cell

Transient analysis of CML and CMOS inverters using Monte Carlo simulation

Use of Electrothermal Simulation to Analyze Thermal Breakdown on N+/P/P+ Diode During ESD Pulse

Application of 2D-Hydrodynamic Energy Modelling to the Optimization of Planar-Doped pseudomorphic HEMTs

Low Frequency Noise and Excess Currents Due to Trap-Assisted Tunneling in Double Barrier Resonant Tunneling Diodes

2D Numerical Investigation of Gate Structure, Band Alignment and Delta-Doping Effects on the Transconductance and Cutoff Frequency of Submicron Si/SiGe FET's

p-MOSFETs and MODFETs with a strained Si channel layer

Reduced Hot Electron Degradation Using Delta-Doped MOSFETs

Dark Current Characterization in CCD's

A High Density Multi-Bit/Analog DRAM Cell

Optimization of a submicron HIMOS Flash $E^{2}PROM$ cell for implementation in a virtual ground array configuration

Temperature Cross-Over Effect of Carrier Avalanche Induced by Band-to-Band Tunneling in ULSI Devices

Field isolation for the Gigabit era devices

0.25 μmCMOS with $N_{2}O$ nitrided gate oxides

Thermal Oxidation of Lightly- and Heavily-Doped Silicon in Pure NO

Comparison of RTP NO-and NH-Nitrided Thin SiO Films

A new optimized process for low pressure nitridation of thin thermal gate oxide

Reduction of Bulk Oxide Trapping in poly-Si Gated MOS Capacitors by Fluorination

Hot Carrier Monitoring in NMOS Transistors by Visible Light Emission

Pulsed Drain Current : A Highly Sensitive Technique for Interface Characterization in VLSI MOSFET's

Simultaneous Measurement of Carrier Mobility and Recombination Lifetime on a Testchip in MOS-Technology by means of the Shockley-Haynes-Experiment within the Temperature Range 98 K to 398 K

A Compact Method for Measuring Parasitic Resistances in Bipolar Transistors

Impact Ionization Effect in Complementary CHarge Injection Transistor

InP Channel HFETs with High Breakdown Voltage and Low Channel Noise

DC Characterization and Low-Frequency Noise in δ-, Pulse- and Uniformly-doped GaAs/AIGaAs MODFETs

Current transient spectroscopy on AlInAs/GaAlInAs heterojunction field effect transistors

DC Characterization of GaP/GaAs Insulated-Gate Inverted-Structure HEMT Grown by Gas Source Molecular Beam Epitaxy (GSMBE)

A Piezo-Electric Field Effect Transistor (PEFET) using AlAs/GaAs strained layer structure on (111)B GaAs substrate

Numerical investigation of leakage current of Schottky contacts on InAlAs/InGaAs/InP heterostructures

Pd-Ge based Ohmic Contacts to InGaAs-InAlAs High Electron Mobility Transistors

Relationship between the 200-mm wafer size and the sub micron technologies

Comparison of Ti and Ni salicides as regards the electrical conductance of silicided films

Selective CVD TiSi for Sub-0.5 μm N+/P+ CMOS Devices

High Resolution Delineation of Bi-dimensional Dopant Profiles in Silicon: Early Stages of Diffusion from Cobalt Silicide Layers

Electrophysical parameters of the SiO-Si system at very high temperatures

Electrical Properties of Thin Oxides for MOSFETs in the Poly-Si / SiO / 6H Silicon Carbide System

STORM: A European Platform for Sub-Micron Technology Simulation and Optimisation

CMOS Device Architecture and Technology for the 0.25 Micron to 0.025 Micron Generations

Characterization of Semiconductor Device Structures with Ultrathin Layers by Raman Scattering

Charge Pumping At Cryogenic Temperatures

Cryogenic on-chip high frequency device characterization

Observation and Modelling of the Gate-Source Capacitance Overshoot in Polysilicon TFTs

Two-dimensional profiling of doped layers bD spreading resistance measurements and atomic force microscopy on chemical etched surfaces

A Comprehensive Analysis of the Relaxation Phenomena in MOSFET's after Uniform Fowler-Nordheim Injection

The ADEQUAT project for development and transfer of 0.25 μm logic CMOS modules

Chemical Mechanical Polishing for Planarisation of Advanced IC Processes

The effect on overlay of wafer distortion induced by dielectric reflow process

Raman spectroscopy measurement of local stress induced by LOCOS and trench structures in the silicon substrate

Double Polysilicon Capacitors in 1 μm Analogue CMOS Technology

Status, Trends, Comparison and Evolution of EPROM and FLASH EEPROM Technologies

Effect of Polysilicon Doping and Oxidation Conditions on Tunnel Oxide Performance For EEPROM Devices

Analysis of the Fabrication Process of Multilayer Vertical Stacked Capacitors

A New Very High Density Full Feature EEPROM Cell with minimum Process Complexity

Charge trapping/detrapping in Si stacked dielectric layer deposited by LPCVD with in situ HF vapor cleaning

Numerical Simulation of Non-Volatile Memories

Simulation of non-equilibrium transport in deep submicron MOSFETs

Performance in RF Power MOSFET's Device For GSM Radiotelephony.

A Physically Based DC-and AC-Model for Vertical Smart Power DMOS Transistors

Weak inversion models for nMOS gate-all-around (GAA) devices

The Influence of Technological Parameters on Ultra-Short Gate SI-NMOS Transistor Performances

Physical Modeling Of Nanoelectronic Devices

Issues in the design of Heterojunction Bipolar Transistors for large signal analogue and high effliciency microwave power

Safe Operating Current Density and Failure modes of Carbon doped base AlGaAs/GaAs HBTs

A New GaAlAs-GaInP-GaAs HBT Technology for Digital and Microwave Applications

Rapid, On-line Extraction of Base Resistance of HBTs and Correlation with Minimum Noise Figure

Highly Sensitive Gated InGaAs/InP Hall Sensors With Low Temperature Coefficient of the Sensitivity

Physics of AlGaAs/InGaAs/GaAs heterostructures for high performance magnetic sensors

SAW transduction technique for GaAs microelectronics compatible acoustoelectronic devices

SOI Technology Outlook for Sub-0.25 μm CMOS, Challenges and Opportunities

Analysis of Carrier Transport and Heating in Ultra-Small SOI N-MOSFETs

A 6 device SOI new technology for mixed analog-digital and rad-hard applications

High frequency bipolar transistor on SIMOX

High-Temperature Gate Capacitances of Thin-Film SOI MOSFETs

Evaluation of CMOS/SOI Devices on Plasma-Thinned Bonded Silicon Wafers

Self-Heating effects on Static and Dynamic SOI Operation

BICMOS: Status and Future Trends

Overview on Active Matrix Display Technology

Reliability modelling with respect to circuit applications

Noise figure degradation under emitter-base reverse stress for high-frequency bipolar ICs

A New Intrinsic charge loss analysis on 16 Mb EPROM

Electrical Performances of a Mounted Chip in a Plastic Package

Diffusion-Induced Degradation of AlGaAs/GaAs Heterojunction Bipolar Transistors by Thermal Stress

Novel Quantum Effect Devices for Future Functional Logic Gates

Performance of 0.2 μm planar doped pseudomorphic and lattice matched HEMTs on GaAs and InP

Physical behaviour of pseudomorphic HEMTs at low temperatures

Broad Transconductance Plateau Region and High Current GaAs/InGaAs Pseudomorphic HENT's Utilizing A Graded In GaAs Channel

Characterization of InAlAs/InGaAs HFETs with High Indium Content in the Channel Grown on GaAs Substrate

Twin-Channel (P and N) CCD Image Sensor with Cross Anti-Blooming

Cross-Sensitivity Elimination in a 3-Dimensional Magnetic Sensor

Study of a new SiO etching process allowing deep and anisotropic trenches. Optimization of new reactor parameters by means of actinometry.

Silicon Bulk Machining of Electrostatic Micromotors Fabrication and Potential Applications

Model of detection for a modulated conductivity sensor: application for a NO gas sensor

Channel Waveguides Through Silicon Wafers for Optically Coupled 3D Integrated Circuits

Physical Mechanisms of Hot-Carrier-Induced Degradation in Deep-Submicron MOSFETs

Design and Characterisation of the Well module for a 6 transistor CHOS SRAM cell in a 0.5 μ=m lithography CMOS technology

Reliability of 0.35 μm Devices: Impact of Ultra-Shallow LDD-Source/Drains

The Gate-to-drain Overlap Effects on the Hot-carrier Induced Degradation of LDD P-channel MOSFET's

Effects of drain engineering on 0.35 μm NMOS Hot-Carrier degradation

Radiation hardness of a bonded silicon-vacuum-silicon field effect structure with 0.1 MGy capability

Detailed Analysis of Buried Oxide Degradation Induced by Hot-Carrier Injection

Comparative study of hot-carrier degradation in $p^{+}$ and $n^{+}$ poly p-MOSFET's of a 0.5 μm CMOS technology

Gate-Voltage Dependence of the Hot-Carrier Degradation of Large-Angle-Tilt Implanted Drain (LATID) and Standard LDD N-Mosfet's

Microwave optical links: A new generation of optoelectronic integrated circuits

Burst Noise And Tunneling Currents In Lattice-Mismatched InP/InGaAs/InP Photodetector Arrays.

First demonstration of nanosecond photon timing in the near-infrared with InGaAs/InP detectors

Structural optimization of quantum confined Stark shift in InGaAs/InGaAsP quantum wells

Extrinsic GaAs:Mn Depectors for. 8 - 12 μm

Linewidth and Mode Structure of Proton-Implanted Vertical Cavity Laser Diodes

Output Characteristics of Surface Emitting Laser Diodes with Short External Cavity

A novel surface emitting GaAs/AIGaAs laser diode beam steering device based on surface mode emission

High Power Vertical Cavity Laser Diodes

An Intelligent 600 V Vertical IGBT on SIMOX Substrate

A Novel MCT Structure For Power Integrated Cirluits

Optimisation of High Voltage (1200 V) MOS Transistor: Voltage Handling Capabilities and Switching Behaviour

Investigation of a Novel Wiring Scheme for 700-1000-V HVIC's

On P-I-N Diode Parameters and Static Properties at Elevated Temperatures and High Current Densities-Experiment vs. Simulation

Overvoltage Protection with a CMOS-Compatible BJT

A New Lateral NPN Transistor Structure for Power MOSFETs with On-Chip Protection

General Introduction, Motivation and Requirements for LV-LP IC's

Opportunities for Scaling FET's for Gigascale Integration (GSI)

Design of Low-Voltage Low-Power IC's

Technology and Device Design Constraints for Low Voltage-Low Power Sub-0.1 μm CMOS Devices

Performance, Reliability, and Supply Voltage Reduction, with the Addition of Temperature as a Design Variable

Low Voltage and Low Power Issues and Applications

``PACT'' - A Programmable Analog CMOS Transmission Circuit for Electronic Telephone Sets

ESSDERC '92: 22nd European Solid State Device Research conference

ESSDERC '91: 21st European Solid State Device Research Conference

ESSDERC '90: 20th European Solid State Device Research Conference

ESSDERC '89: 19th European Solid State Device Research Conference

ESSDERC '88: 18th European Solid State Device Research Conference

ESSDERC '87: 17th European Solid State Device Research Conference

0.25 μmCMOS with $N_{2}O$ nitrided gate oxides

Content Provider	IEEE Xplore Digital Library
Author	Pomp, H.G. Lifka, H. Paulzen, G. Montree, A.H. Woerlee, P.H. Woltjer, R.
Copyright Year	1993
Description	Author affiliation: Philips Res. Labs., Eindhoven, Netherlands (Pomp, H.G.; Lifka, H.; Paulzen, G.; Montree, A.H.; Woerlee, P.H.; Woltjer, R.)
Abstract	For a 0.25 μm CMOS process a simple and compatible two-step $N_{2}O$ nitridation technology was developed. High quality dielectrics were obtained for both surface channel PMOS and NMOS devices. The use of the nitridation technology improves the gate oxide quality considerably. Furthermore the technology enables the use of $BF_{2}^{+}$ for gate and drain doping of the PMOS devices. The hot carrier degradation measured at worst case condition $(V_{ga}$ = $l/2V_{ds}),$ results in a slight improvement of lifetime of PMOS devices.
Starting Page	399
Ending Page	402
File Size	323964
Page Count	4
File Format	PDF
ISBN	2863321358
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-09-13
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Editions Frontieres
Subject Keyword	MOS devices CMOS technology Dielectric devices Boron Oxidation Annealing Threshold voltage Transconductance CMOS process Furnaces
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in