NDLI: A 500-Picosecond System Design Capability

Content Provider	IEEE Xplore Digital Library
Author	Hollock, S.
Copyright Year	1979
Description	Author affiliation: Plessey Research (Caswell) Limited, Allen Clark Research Centre, Caswell, Towcester, Northamptonshire NN12 8EQ, U.K. (Hollock, S.)
Abstract	A family of ultra-high speed devices has been designed to maximise the performance of digital systems. The family is based on MSI parts developed on the high performance Plessey Process III(V); these circuits offer local gate delays of 500 picoseconds and flip-flop clock rates of over 500 MHz, and enable overall `system' gate delays of less than one nanosecond to be achieved. The performance of a scaled version of one of these circuits has improved these gate delays by a further 150 picoseconds; this improvement has been achieved by the reduction of minimum geometries to three microns. By the introduction of fundamental improvements to the basic transistor structure, and by optimisation of geometries, it will be possible to reduce the local gate delay to 200 picoseconds and the system gate delay to 500 picoseconds.
Starting Page	79
Ending Page	81
File Size	1609878
Page Count	3
File Format	PDF
ISBN	0852962088
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-09-18
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	The Institution of Electrical Engineers
Subject Keyword	Circuits Logic arrays Digital systems Flip-flops Clocks Delay systems Geometry Logic devices Propagation delay Logic gates
Content Type	Text
Resource Type	Article

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