NDLI: A 40Mbit/s Soft-Output Viterbi Decoder

Content Provider	IEEE Xplore Digital Library
Author	Joeressen, Olaf J. Meyr, Heinrich
Copyright Year	1994
Description	Author affiliation: RWTH Aachen, Integrated Systems for Signal Processing, ISS - 611810, Templergraben 55, D-52056 Aachen, Germany. Tel: + 49-241-807632 (Meyr, Heinrich) \|\| RWTH Aachen, Integrated Systems for Signal Processing, ISS - 611810, Templergraben 55, D-52056 Aachen, Germany. Tel: + 49-241-807632, email: joeresse@ert.rwth-aachen.de (Joeressen, Olaf J.)
Abstract	Soft output decoding has evolved as a key technology for new error correction approaches with unprecedented performance as well as for improvement of well established transmission techniques. In this paper we present, to the best of our knowledge, the first high speed VLSI implementation of the soft output Viterbi algorithm, a low complexity soft output algorithm. The $43mm^{2}$ chip is designed for a 16 state convolutional code, and tested samples achieved a throughput of 50 Mbit/s. The chip is roughly twice as big as a Viterbi decoder without soft outputs. It is thus shown with the design that transmission schemes using soft output decoding can be considered practical even at very high throughput.
Starting Page	216
Ending Page	219
File Size	736591
Page Count	4
File Format	PDF
ISBN	2863321609
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-20
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Editions Frontieres
Subject Keyword	Viterbi algorithm Decoding Throughput Error correction Signal processing algorithms Testing Application specific integrated circuits Wiring Signal processing Very large scale integration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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