NDLI: SLOCOP-II: Improved accuracy and efficiency in Timing Verification, based on logic functionality and MOS circuit hierarchy

Content Provider	IEEE Xplore Digital Library
Author	Johannes, P. Das, P. Claesen, L. De Man, H.
Copyright Year	1989
Description	Author affiliation: IMEC Kapeldreef 75, B-3030 Leuven (Belgium) (Johannes, P.; Das, P.; Claesen, L.) \|\| IMEC Kapeldreef 75, B-3030 Leuven (Belgium); Professor at Katholieke Universiteit Leuven Belgium (De Man, H.)
Abstract	The new SLOCOP-II timing verifier for MOSVLSI circuits is presented. Existing timing verifiers do not take into account the logic functionality and can give rise to serious overestimates for the circuit delays. In SLOCOP-II new false path avoidance algorithms have been implemented taking into account the logic functionality of the circuits. For the purpose of generality new methods for event determination have been developed and are presented in this paper. The circuit hierarchy is exploited in order to allow for faster evaluations. Timing verification results are given for instances of the parameterised modules in the CATHEDRAL-II library.
Starting Page	248
Ending Page	251
File Size	554987
Page Count	4
File Format	PDF
ISBN	3854031017
DOI	10.1109/ESSCIRC.1989.5468072
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-09-20
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Logic circuits Propagation delay Software libraries Very large scale integration Circuit simulation Digital systems Multiplexing Delay effects Pattern matching
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

SLOCOP-II: a versatile timing verification system for MOSVLSI

A Timing Verification System Based on Extracted MOS/VLSI Circuit Parameters

Macromodeling of Digital MOS VLSI Circuits

Switch-Level Delay Models for Digital MOS VLSI

Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

Timing accuracy in VLSI testing

An accurate timing model for fault simulation in MOS circuits

A Multiple Media Delay Simulator for MOS LSI Circuits

On the use of hierarchy in timing verification with statically sensitizable paths

SLOCOP-II: Improved accuracy and efficiency in Timing Verification, based on logic functionality and MOS circuit hierarchy

Similar Documents

SLOCOP-II: a versatile timing verification system for MOSVLSI

A Timing Verification System Based on Extracted MOS/VLSI Circuit Parameters

Macromodeling of Digital MOS VLSI Circuits

Switch-Level Delay Models for Digital MOS VLSI

Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

Timing accuracy in VLSI testing

An accurate timing model for fault simulation in MOS circuits

A Multiple Media Delay Simulator for MOS LSI Circuits

On the use of hierarchy in timing verification with statically sensitizable paths

SLOCOP-II: Improved accuracy and efficiency in Timing Verification, based on logic functionality and MOS circuit hierarchy