NDLI: An Experimental 1.8 μm CMOS Anti-Aliasing Switched-Capacitor Decimator with High Input Sampling Frequency

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Volume 2 - 1991

Volume 1 - 1991

Seventeenth European Solid State Circuits Conference

Honorary Chairman

Conference Chairman

Program Committee Chairman

Technical Program Committee

Foreword [to the ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference]

Table of contents

Balanced Integrator Filters at Video Frequencies

High Performance OTA-R-C Continuous-Time Filters with Full CMOS Low Distortion Floating Resistors

8-32MHz Tunable BICMOS Continuous-Time Filter

An Experimental 1.8 μm CMOS Anti-Aliasing Switched-Capacitor Decimator with High Input Sampling Frequency

Experimental Investigation of the Minimum Signal of DRAM Cells for Reliable Operation of Sense Amplifiers

A 34ns 16MbDRAM with controllable voltage down convertor

Sense-Amplifier-Merged Comparator and Selector Scheme for BiCMOS Cache Memories

Deep Sub-Micron BICMOS Circuit Technology for Sub-10 ns ECL 4-Mb DRAMs

A Highly Flexible ROM Generator for BiCMOS Technology

TOPICS: A New Hierarchical Design Tool using an Expert System and Interval Analysis

DC Analysis of Non-Linear Circuits using Solution Tracing Circuits

Injectable biotelemetry CMOS chip for identification and temperature measurement system

A Single Chip 135MHz CMOS Colour Video Controller

A Hybridised, Charged-Particle Multidetector

A general digital signal processor in 1.2 μM Cmos with on chip D/A and A/D conversion for use in a GSM handportable terminal

An Interface Circuit for Contactless Power and Data Transmission for Chipcard and Identification Systems

A Class AB High Swing CMOS Power Amplifier

Low Noise Tape Preamplifier with New Self-Biasing Architecture

A Novel Output Structure for CMOS Power Amplifiers

Gigahertz Amplifiers in Fine Line CMOS-Technology

A low noise Amplifier with Automatic Gain Control and Anti Clipping Control in CMOS Technology

A Configurable Convolution Chip with Programmable Coefficients

Semi-systolic architecture with carry-save arithmetic for binary correlators in spread-spectrum-systems

Systolic Array Architecture for Early Vision Processing

A Novel Bit-Level Systolic Array Median Filter

A New Architecture for an Automatic Generation of Fast Pipelined Adders

A High-Performance Iμm CMOS Current Controlled Oscillator

A 4 Gs/s and 10 mV Latched Comparator in 0.5 μm GaAs HEMT Technology

Fully-Bipolar 120 MHz, 10-bit Track & Hold Circuit

A 45MHz VCO Combining High Linearity With High Modulation Bandwidth

A New HF VCO With Quadrature Outputs

Complex 3D-CMOS Circuits based on a Triple-Decker Cell

A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization

A 200 MHz CMOS Driver with Output Impedance Automatic Control

Optimization of Buffer Stages in Bipolar VLSI Systems

A CMOS Off-Chip Driver/Receiver with Reduced Signal Swing and Reduced Power-Supply Disturbance

A Multichip CMOS RISC Processor with Low-Voltage Swing Inputs and Outputs

A 16×16 bits Multiplier in 0.5μm CMOS technology

VLSI System Design for automotive Control

Bit-Serial Correlator with Novel Clocking Scheme

System Integration for Baseband Processing in the Pan-European Digital Mobile Radio System

Design and Applications of Tunable Analog BiCMOS Circuits

Low Output-Offset Variation S/H Circuits for An LCD Segment Driver IC Achieving Wide Signal Frequency Bandwidth

Application of Bridged T-coils to the Design of Multiplicative Gain MMIC Amplifiers

A Novel CMOS Interface for Oxygen Sensors

Multifunction Voltage Regulator for the automotive environment

Design of Analog Neural Programmable Optimizers in CMOS VLSI Technologies

A Floating Point cell library for a 100MFLOPS Image Signal Processor

Random Access Analog Memory for Early Vision

A Cost/Error computing circuit for HDTV coding

Complexity Estimation for Real Time Application Specific Circuits

Test Strategy For The Signal Processor KISS16

On-Chip Test Circuitry for a 2 ns Cycle 512Kb CMOS ECL SRAM

Current versus Voltage Testing of Bridging Defects in a Dual Port Memory Cell

Block-Oriented Test-Strategy for Analog Circuits

JTAG SRAM Tester Chip

A 125 MHz Monolithic Transceiver Interface for Fiber Distributed Data Interface

A Submicron NMOS Multiplexer-Demultiplexer Chip Set for 622 Mb/s SONET Applications

Eight Channel Parallel Speech Transmission Circuit

A Multifunctional High Speed Switching Element for ATM Applications

Practical Design Techniques for 16-Bit CMOS A/D Delta-Sigma Converter

A CMOS 13 bits Cyclic RSD A/D Converter

A Fourth-Order ΣΔ Converter with Self-Tuning Continuous Time Noise Shaper

A multiplying DAC using a Sigma-Delta Modulator

A Low-Noise Trunk Interface Circuit

A 1GHz Single Chip Quadrature Modulator without External Trimming

A High Speed CMOS Circuit for 1.244 Gb/s 16×16 ATM Switching

A 320 Mb/s CMOS Directly Driven Transmission Circuit System Using Twisted Pair Cables

Integrated Instrumentation Amplifier for the Phase-Readout of a Piezoresistive Smart Sensor

A Smart Image Sensor for Computer Vision

On-chip Automatic Exposure Control Technique

Integrated Bipolar Circuit for the Readout of a Capacitive Torque Sensor

ESSCIRC '90: Sixteenth European Solid-State Circuits Conference

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

ESSCIRC '88: Fourteenth European Solid-State Circuits Conference

ESSCIRC '87: 13th European Solid-State Circuits Conference

ESSCIRC '86: Twelfth European Solid-State Circuits Conference

ESSCIRC '85: 11th European Solid-State Circuits Conference

ESSCIRC '84: Tenth European Solid-State Circuits Conference

ESSCIRC '83: Ninth European Solid-State Circuits Conference

ESSCIRC '82: Eighth European Solid-State Circuits Conference

ESSCIRC '81: 7th European Solid State Circuits Conference

ESSCIRC 80: 6th European Solid State Circuits Conference

Fifth European Solid State Circuits Conference - ESSCIRC 79

ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers

ESSCIRC '77: 3rd European Solid State Circuits Conference

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1975 First European Solid State Circuits Conference (ESSCIRC)

An Experimental 1.8 μm CMOS Anti-Aliasing Switched-Capacitor Decimator with High Input Sampling Frequency

Content Provider	IEEE Xplore Digital Library
Author	Martins, R.P. Franca, J.E. Maloberti, F.
Copyright Year	1991
Description	Author affiliation: University of Pavia, Department of Electronics, Via Abbiategrasso, Pavia, Italy. (Maloberti, F.) \|\| Instituto Superior Técnico, Department of Electrical and Computer Engineering, Av. Rovisco Pais, 1, 1096 Lisboa Codex, Portugal. (Martins, R.P.; Franca, J.E.)
Abstract	An optimum anti-aliasing switched-capacitor (SC) decimator is capable of achieving a high input sampling ratio while employing operational amplifiers operating at a much lower frequency than what would be needed in conventional SC filtering circuits. This is demonstrated considering the design of a 2nd. order SC decimator building block which has been realised in a 1.8μm CMOS double-poly technology, and achieves a frequency decimation capability from 16.59MHz to 5.53MHz with a total power consumption of only 1.75 mW. The experimental evaluation of the resulting performance behavior has been carried-out not only with respect to the non-ideal characteristics of the amplifiers but also with respect to the errors which may occur associated with the switch timing controlling the operation of the circuit.
Starting Page	13
Ending Page	16
File Size	1516382
Page Count	4
File Format	PDF
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-09-11
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Tecniche Nuove
Subject Keyword	Sampling methods Frequency Switching circuits Operational amplifiers CMOS technology Switches Filtering Energy consumption Error correction Timing
Content Type	Text
Resource Type	Article

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