NDLI: A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

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Proceedings contents

ESSDERC/ESSCIRC Steering Committee

ESSDERC/ESSCIRC Technical Programme Committee

Joint plenary talks

ESSCIRC Table of contents

Emerging device nanotechnology for future high-speed and energy-efficient VLSI: Challenges and opportunities

Micropower energy scavenging

Solving issues of integrated circuits by 3D-stacking meeting with the era of power, integrity attackers and NRE explosion and a bit of future

Printed electronics for low-cost electronic systems: Technology status and application development

SOI design in Cell Processor and beyond

Information, energy, and entropy: Design principles for adaptive, therapeutic modulation of neural circuits

Audio at low and high power

Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node

Area/yield trade-offs in scaled CMOS SRAM cell

A monolithic step-down SC power converter with frequency-programmable subthreshold z-domain DPWM control for ultra-low power microsystems

A fully-integrated 130nm CMOS DC-DC step-down converter, regulated by a constant on/off-time control system

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM

A time-domain SAR smart temperature sensor with −0.25∼+0.35°C inaccuracy for on-chip monitoring

A temperature-to-digital converter based on an optimized electrothermal filter

A fully integrated interface circuit for 1.5°C accuracy temperature control and 130-dB dynamic-range read-out of MOX gas sensors

A 0.17–1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS

A 15 MHz – 600 MHz, 20 mW, 0.38 $mm^{2},$ fast coarse locking digital DLL in 0.13μm CMOS

A $0.042-mm^{2}$ fully integrated analog PLL with stacked capacitor-inductor in 45nm CMOS

A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution

24-GHz 1-V pseudo-stacked mixer with gain-boosting technique

A 65-nm CMOS 8-GHz injection locked oscillator for HDR UWB applications

A 600-GHz CMOS focal-plane array for terahertz imaging applications

Single-photon synchronous detection

Highly sensitive UV-enhanced linear CMOS photosensor

A 3-TFT hybrid active-passive pixel with correlated double sampling CMOS readout circuit for real-time medical x-ray imaging

On-chip jitter and oscilloscope circuits using an asynchronous sample clock

CMOS unclonable system for secure authentication based on device variability

Circuit techniques for suppression and measurement of on-chip inductive supply noise

A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface

A low power CMOS SAW-less quad band WCDMA/HSPA/1X/EGPRS transmitter

A 14-mW 2.4-GHz CMOS transceiver for short range wireless sensor applications

A multi-standard mobile digital video receiver in 0.18μm CMOS process

On-chip auto-calibrated RF tracking filter for cable silicon tuner

Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode

5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS

A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery

A low-jitter 1.5-GHz and 350-ppm spread-spectrum serial ATA PHY using reference clock with 400-ppm production-frequency tolerance

An adaptive 4-tap analog FIR equalizer for 10-Gb/s over backplane serial link receiver

A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS

Standby power reduction techniques for ultra-low power processors

Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core

A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network

Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications

A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS

A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range

A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm

Third-order ΣΔ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW

Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs

A multiword based high speed ECC scheme for low-voltage embedded SRAMS

Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield

A robust single supply voltage SRAM read assist technique using selective precharge

A 90nm CMOS mm-wave VCO using an LC tank with inductive division

A fully integrated 60 GHz transmitter front-end with a PLL, an image-rejection filter and a PA in SiGe

60GHz quadrature doppler radar transceiver in a 0.25μm SiGe BiCMOS technology

A 60GHz digitally controlled phase shifter in CMOS

A 71–73 GHz voltage-controlled standing-wave oscillator in 90 nm CMOS technology

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS

A 90nm 8b 120Ms/s-250Ms/s pipeline ADC

A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications

An 8-bit Flash Analog-to-Digital Converter in standard CMOS technology functional in ultra wide temperature range from 4.2 K to 300 K

A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability

A reconfigurable 65nm SRAM achieving voltage scalability from 0.25–1.2V and performance scalability from 20kHz–200MHz

A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis

A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage

Current reuse CMOS LNA for UWB applications

A UWB transformer-C orthonormal state space band-reject filter in 0.13 μm CMOS

A 9mW high band FM-UWB receiver front-end

A low-voltage mobility-based frequency reference for crystal-less ULP radios

A 36V precision programmable gain amplifier with CMRR exceeding 120dB in all gains

A 65-nm 84-dB-gain 200-MHz-UGB CMOS fully-differential three-stage amplifier with a novel Common Mode control

A CMOS source-buffered differential input stage with high EMI suppression

Analog signal processing for a class D audio amplifier in 65 nm CMOS technology

Reduction of VCO phase noise through forward substrate biasing of switched MOSFETs

A WiMedia UWB receiver with a synthesizer

An ultra low power and high efficiency UWB transmitter for WPAN applications

A 3–10 GHz flexible CMOS LO generator for MB-OFDM UWB application using wide tunable VCOs

0.13 μm CMOS Cartesian loop transmitter IC with fast calibration and switching scheme from opened to closed loop

Low drop-out voltage regulator with full on-chip capacitance for slot-based operation

High-performance low-dropout regulator achieved by fast transient mechanism

A high-power-LED driver with power-efficient LED-current sensing circuit

Boost DC-DC converter with charge-recycling (CR) and fast reference tracking (FRT) techniques for high-efficiency and low-cost LED driver

An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DAC

Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction

A low-power programmable dynamic frequency divider

Supply-noise mitigation techniques in phase-locked loops

A 46pJ/pulse analog front-end in 130nm CMOS for UWB impulse radio receivers

A 7.5mA 500 MHz UWB receiver based on super-regenerative principle

Low-Power CMOS RF front-end for non-coherent IR-UWB receiver

Super-regenerative UWB impulse detector with synchronized quenching mechanism

A fully-integrated Wienbridge topology for ultra-low-power 86ppm/°C 65nm CMOS 6MHz clock reference with amplitude regulation

A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits

Electronic interface for Piezoelectric Energy Scavenging System

A 0.2V–1.2V converter for power harvesting applications

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS

A 1.2V receiver front-end for multi-standard wireless applications in 65 nm CMOS LP

A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner

A fractional spur reduction technique for RF TDC-based all digital PLLs

An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications

A $0.23mm^{2}$ free coil ZigBee receiver based on a bond-wire self-oscillating mixer

An ultra low power GFSK demodulator for wireless body area network

A 3∓5 GHz low-complexity ultra-wideband CMOS RF front-end for low data-rate WPANs

A 828μW 1.8V 80dB dynamic-range readout interface for a MEMS capacitive microphone

A low-power capacitance to pulse width converter for MEMS interfacing

A 14 - bit micro-watt power scalable automotive MEMS pressure sensor interface

A high gain-bandwidth product transimpedance amplifier for MEMS-based oscillators

A synchronous chopping technique and implementation for high-frequency precision sensing

A 211 GOPS/W dual-mode real-time object recognition processor with Network-on-Chip

A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals

2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE

An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx

Implementation of a phase-encoding signalling prototype chip

A high-resolution 24-dBm Digitally-Controlled CMOS PA for multi-Standard RF polar transmitters

A 1.2V, 17dBm digital polar CMOS PA with transformer-based power interpolating

A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process

0.13-μm SiGe BiCMOS radio front-end circuits for 24-GHz automotive short-range radar sensors

A 24GHz FMCW radar transmitter in 0.13 μm CMOS

A 45nm single power supply SRAM supporting low voltage operation down to 0.6V

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A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

Content Provider	IEEE Xplore Digital Library
Author	Gharbiya, A. Johns, D.A.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON (Gharbiya, A.; Johns, D.A.)
Abstract	A 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth is implemented in 0.18 mum CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).
Starting Page	206
Ending Page	209
File Size	578141
Page Count	4
File Format	PDF
ISBN	9781424423613
ISSN	19308833
e-ISBN	9781424423620
DOI	10.1109/ESSCIRC.2008.4681828
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-15
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bandwidth Multi-stage noise shaping Delta modulation Topology Stability Quantization Noise generators CMOS technology Feedback Transfer functions
Content Type	Text
Resource Type	Article

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