NDLI: 10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver

Content Provider	IEEE Xplore Digital Library
Author	Francese, P.A. Toifl, T. Braendli, M. Menolfi, C. Kossel, M. Morf, T. Kull, L. Andersen, T.M. Yueksel, H. Cevrero, A. Luu, D.
Copyright Year	2015
Description	Author affiliation: IBM Zurich, Rüschlikon, Switzerland (Francese, P.A.; Toifl, T.; Braendli, M.; Menolfi, C.; Kossel, M.; Morf, T.; Kull, L.; Andersen, T.M.; Yueksel, H.; Cevrero, A.; Luu, D.)
Abstract	The authors report the implementation of a continuous-time linear equalizer (CTLE) featuring a new technique to control the high-frequency gain peaking and to interface to current-summing stages usually implemented as interleaved slices for the linear analog superposition of the coefficients of decision-feedback equalizers (DFE). The circuits are implemented in 14nm FinFET SOI CMOS technology and are included in a prototype receiver targeted to 16Gb/s serial I/O links for multi-core microprocessors off-chip communication. The architecture is shown in the paper. Power efficiency and compactness are among the primary goals of the study together with an equalization capability sufficient to recover at bit-error rate (BER) levels below $10^{-12}$ data transmitted across smooth channels with losses in excess of 25dB at 8GHz.
Starting Page	1
Ending Page	3
File Size	751567
Page Count	3
File Format	PDF
ISBN	9781479962235
e-ISBN	9781479962242
DOI	10.1109/ISSCC.2015.7062988
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Receivers Decision feedback equalizers CMOS integrated circuits Gain measurement Bit error rate
Content Type	Text
Resource Type	Article

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