NDLI: A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine

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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Copyright [2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers]

Table of contents

SE1 Digitally Enhanced Analog & RF

SE2 Circuit Design in the Year 2012

Session 1 Overview: Plenary Session

Foundry Future: Challenges in the 21st Century

Analog and Mixed-Signal Innovation: The Process-Circuit-System-Application Interaction

Towards a New Nanoelectronic Cosmology

Optical Communications

A Fully Integrated 4×10Gb/s DWDM Optoelectronic Transceiver in a standard 0.13/spl mu/m CMOS SOI

A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects

A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

A CMOS Burst-Mode TIA with Step AGC and Selective Internally Created Reset for 1.25Gb/s EPON

A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation

A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS

A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation

A Fractional-N PLL for SONET-Quality Clock-Syntlhesis Applicationis

TD: Emerging Devices Devices and Circuits

Efficient Power Management Circuit: Thermal Energy Harvesting to Above-IC Microbattery Energy Storage

Minimum Energy Tracking Loop with Embedded DC-DC Converter Delivering Voltages down to 250mV in 65nm CMOS

LAGS System Using Data/Instruction Grain Power Control

Gate Work Function Engineering for Nanotube-Based Circuits

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

An Organic Imager for Flexible Large Area Electronics

Passive-Matrix Flexible Electronic Paper Using Quick-Response Liquid Powder Display (QR-LPD) Technollogy and Custom Driver Circuits

RF Building Blocks

A Digitally Modulated Polar CMOS PA with 20MHz Signal BW

A 3W 55% PAE CMOS PA with Closed-Loop 20:1 VSWR Protection

Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar Transmitters

A Blocker Filtering Technique for Wireless Receivers

A 0.13μm 1.5V CMOS I/Q Downconverter with Digital Adaptive IIP2 Calibration

A Delay-Line-Based GFSK Demodulator for Low-IF Receivers

A 4.5GHz LC-VCO with Self-Regulating Technique

A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning

Microprocessors

Design of the Power6 Microprocessor

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption

An Integrated Quad-Core Opteron Processor

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

The Implementation of the 65nm Dual-Core 64b Merom Processor

An 8-Core 64-Thread 64b Power-Efficient SPARC SoC

UWB and mm-Wave Communications Systems

A WiMedia-Compliant UWB Transceiver in 65nm CMOS

A 0.18/spl mu/m CMOS Dual-Band UWB Transceiver

A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS

A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a

A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver

A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable-Phase Ring Oscillator and PLL Architecture

A Bandpass ΔΣ DDFS-Driven 19GHz Frequency Synthesizer for FMCW Automotive Radar

Display Electronics

An 8b Source Driver for 2.0 inch Full-Color Active-Matrix OLEDs Made with LTPS TFTs

A 2.6 inch VGA LCD with Optical Input Function using a 1-Transistor Active-Pixel Sensor

An Integrated LDI with Readout Function for Touch-Sensor-Embedded Display Panels

A Single-Inductor Step-Up DC-DC Switching Converter with Bipolar Outputs for Active Matrix OLED Mobile Display Panels

A 10b Driver IC for a Spatial Optical Modulator for Full HDTV Applications

A 16.7M Color VGA Display Driver IC with Partial Graphic RAM and 500Mb/s/ch Serial Interface for Mobile a-Si TFT-LCDs

A Column Driver with Low-Power Area-Efficient Push-Pull Buffer Amplifiers for Active-Matrix LCDs

E1 Ultimate Limits of Integrated Electronics

SE3 Last Mile Access Options: PON/DSL/Cable/Wireless

SE4 Automotive Signal Processing Technologies

Biomedical Devices

A 232-Channel Visual Prosthesis ASIC with Production-Compliant Safety and Testability

A Fully Integrated Digital Hearing-Aid Chip with Human-Factors Considerations

A Non-Coherent PSK Receiver with Interference-Canceling for Transcutaneous Neural Implants

An 11k-Electrode 126-Channel High-Density Microelectrode Array to Interact with Electrogenic Cells

256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes

A 2.2/spl mu/W 94nV//spl radic/Hz, Chopper-Stabilized Instrumentation Amplifier for EEG Detection in Chronic Implants

A Current-Sensitive Front-End Amplifier for Nano-Biosensors with a 2MHz BW

Miniaturization of Magnetic Resonance Microsystem Components for 3D Cell Imaging

A High-Density Magnetoresistive Biosensor Array with Drift-Compensation Mechanism

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI

A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability

All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs

A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology

12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique

Adaptive low-jitter LC-based clock distribution

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

mm-Wave Tranceivers and Building Blocks

A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider

A Highly Integrated 60GHz CMOS Front-End Receiver

A 60GHz Low-Power Six-Port Transceiver for Gigabit Software-Defined Transceiver Applications

A 23-to-29GHz Differentially Tuned Varactorless VCO in 0.13μm CMOS

A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS

A 90GHz 65nm CMOS Injection-Locked Frequency Divider

Low-Power mm-Wave Components up to 104GHz in 90nm CMOS

A Bidirectional RF-Combining 60GHz Phased-Array Front-End

TV Tuner / RFID

A 48-to-860MHz CMOS Direct-Conversion TV Tuner

A SiP Tuner with Integrated LC Tracking Filter for both Cable and Terrestrial TV Reception

A Multi-Standard Analog and Digital TV Tuner for Cable and Terrestrial Applications

A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications

A 900MHz UHF RFID Reader Transceiver IC

A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader

An Integrated RFID Reader

Gigabit CDRs Equalizers

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

A 40-to-44Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver

A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells

Cascading Techniques for a High-Speed Memory Interface

ΔΣ ADCs and Converter Techniques

A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band

A 0.13/spl mu/m CMOS EDGE/UMTS/WLAN Tri-Mode /spl Delta//spl Sigma/ ADC with -92dB THD

A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS

A 5,sup>th-order CT/DT Multi-Mode ΔΣ Modulator

A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS

A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS

A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13/spl mu/m CMOS

Baseband Signal Processing

RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction

A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS

A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip

A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End

A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure

A GSM Baseband Radio in 0.13μm CMOS with Fully Integrated Power-Management

An Integrated Draft 802.11n Compliant MIMO Baseband and MAC Processor

Multimedia and Parrallel Signal Processors

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis

A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS

A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine

A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling

A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip

A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications

Power Distribution and Management

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth

Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor

Analog Techniques and PLLs

A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation

A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS

A 40-to-800MHz Locking Multi-Phase DLL

A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process

A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter

A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz

A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme

A Sub-200mV 6T SRAM in 0.13μm CMOS

Cellular and Multi-Mode Transceivers

Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz Offset

A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR

A WCDMA Transmitter in 0.13μm CMOS Using Direct-Digital RF Modulator

A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13μm CMOS

A Dual-Band CMOS Transceiver for 3G TD-SCDMA

A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

A Polar Loop Transmitter with Digital Interface including a Loop-Bandwidth Calibration System

A Polynomial-Predistortion Transmitter for WCDMA

A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme

TD: Proximity Data and Power Transmission

3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping

An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package

Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches

A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications

A 0.9V 2.6mW Body-Coupled Scalable PHY Transceiver for Body Sensor Applications

Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication

E2 Digital RF Fundamentally a New Technology or Just Marketing Hype?

SE5 Highlights of IEDM 2006

SE6 Secure Digital Systems

SE7 Implantable and Prosthetic Devices: Life-Changing Circuits

Sensors and MEMS

A Wireless Strain Sensing Microsystem with External RF Power Source and Two-Channel Data Telemetry Capability

A CMOS Single-Chip Electronic Compass with Microcontroller

A 100Hz 5nT/Hz Low-Pass /spl Delta//spl Sigma/ Servo-Controlled Microfluxgate Magnetometer Using Pulsed Excitation

A 0.2°/hr Micro-Gyroscope with Automatic CMOS Mode Matching

A 92dB-DR 13mW /spl Delta//spl Sigma/ Modulator for Spaceborn Fluxgate Sensors

A CMOS 2D Micro-Fluxgate Earth Magnetic Field Sensor with Digital Output

An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology

A 128/spl times/2 CMOS Single-Photon Streak Camera with Timing-Preserving Latchless Pipeline Readout

Digital Circuit Innovations

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure

Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops

True Random Number Generator with a Metastability-Based Quality Control

A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations

A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-Chip

High-Speed and Low-Energy Capacitively-Driven On-Chip Wires

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects

Broadband RF and Radar

A Broadband Receive Chain in 65nm CMOS

A 0.13/spl mu/m CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers

An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOS

A 1.4V 25mW Inductorless Wideband LNA in 0.13/spl mu/m CMOS

A 4-Channel UWB Beam-Former in 0.13μm CMOS using a Path-Sharing True-Time-Delay Architecture

Heterodyne Phase Locking: A Technique for High-Frequency Division

A 79GHz SiGe-Bipolar Spread-Spectrum TX for Automotive Radar

A 75-GHz PLL in 90-nm CMOS Technology

Multi-GB/s Transceivers

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output

A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

A 20Gb/s Broadband Transmitter with Auto-Configuration Technique

A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI

Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs

Nyquist ADC Techniques

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing

A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS

A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

A Zero-Crossing-Based 8b 200MS/s Pipelined ADC

A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS

An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration

A 50GS/s Distributed T/H Amplifier in 0.18μm SiGe BiCMOS

A Cryogenic ADC operating Down to 4.2K

Non-Volatile Memories

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current

A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface

A 0.13/spl mu/m 2.125MB 23.5ns Embedded Flash with 2GB/s Read Throughput for Automotive Microcontrollers

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read

A 0.05×0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM

A DLL with Jitter-Reduction Techniques for DRAM Interfaces

A Dual-Line Optical Transient Sensor with On-Chip Precision Time-Stamp Generation

A Spatial-Temporal Multi-Resolution CMOS Image Sensor with Adaptive Frame Rates for Moving Objects in the Region-of-Interest

A Per-Pixel Pulse-FM Background Subtraction Circuit with 175ppm Accuracy for Imaging Applications

A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC

A 1/2.5 inch 8.1Mpixel CMOS Image Sensor for Digital Cameras

A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders

A 2/3 inch CMOS Image Sensor for HDTV Applications with Multiple High-DR Modes and Flexible Scanning

A MOS Image Sensor with Microlenses Built by Sub-Wavelength Patterning

Analog and Power Management Techniques

A 2W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters

A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance

A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories

A 237mW aDSL2+ CO Line Driver in Standard 1.2V 0.13μ CMOS

A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter

A 3MHz Low-Voltage Buck Converter with Improved Light Load Efficiency

A Voltage Regulator for Subthreshold Logic with Low Sensitivity to Temperature and Process Variations

A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter

A Single-Inductor Switching DC-DC Converter with 5 Outputs and Ordered Power-Distributive Control

Building Blocks for High-Speed Transceivers

40Gb/s High-Gain Distributed Amplifiers with Cascaded Gain Stages in 0.18/spl mu/m CMOS

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS

A Self-Calibrated On-chip Phase-Noise-Measurement Circuit with -75dBc Single-Tone Sensitivity at 100kHz Offset

A 10dB 44GHz Loss-Compensated CMOS Distributed Amplifier

A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection

45% Power Saving in a 0.25/spl mu/m BiCMOS 10Gb/s 50/spl Omega/-Terminated Packaged Active-Load Laser Driver

A 240MHz-BW 112dB-DR TIA

A Single-Chip Bluetooth EDR Device in 0.13μm CMOS

A Fully Integrated MIMO Multi-Band Direct-Conversion CMOS Transceiver for WLAN Applications (802.11n)

An 802.11a/b/g RF Transceiver in an SoC

A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dBm Output Power for WLAN Applications

TD: Trends in Wireless Systems

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy

A Low Phase Noise 10GHz Optoelectronic RF Oscillator Implemented Using CMOS Photonics

Advanced MMIC for Passive Millimeter and Submillimeter Wave Imaging

UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems

A 1V 600/spl mu/W 2.1GHz Quadrature VCO Using BAW Resonators

A 1.8V 165mW Discrete Wavelet Multi-Tone Baseband Receiver for Cognitive Radio Applications

A 2GHz 0.25μm SiGe BiCMOS Oscillator with Flip-Chip Mounted BAW Resonator

A Passive UHF RFID Transponder for EPC Gen 2 with -14dBm Sensitivity in 0.13μm CMOS

Timetable of ISSCC 2007 Sessions

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS

F1: Non-Volatile Memory Circuit Design and Technology

Contributor listings

Contributor listings

San Francisco Marriott Hotel Location Maps

ISSCC 2008 Call for Papers

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A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine

Content Provider	IEEE Xplore Digital Library
Author	Seok-Hoon Kim Jae-Sung Yoon Chang-Hyo Yu Donghyun Kim Kyusik Chung Han Shin Lim HyunWook Park Lee-Sup Kim
Copyright Year	2007
Description	Author affiliation: KAIST, Daejeon (Seok-Hoon Kim; Jae-Sung Yoon; Chang-Hyo Yu; Donghyun Kim; Kyusik Chung; Han Shin Lim; HyunWook Park; Lee-Sup Kim)
Abstract	A 3D display processor with a programmable 3D graphics rendering engine is implemented. The integrated rendering engine supports Pixel Shader 3.0 and OpenGL ES 2.0. A 3D image synthesis engine generates 3D images at 36fps. The die contains 1.74M gates and occupies $5times5mm^{2}$ in 0.18mum CMOS and dissipates 379mW at 1.8V.
Starting Page	276
Ending Page	602
File Size	3000423
Page Count	327
File Format	PDF
ISBN	1424408520
ISSN	01936530
DOI	10.1109/ISSCC.2007.373401
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-02-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three dimensional displays Graphics Rendering (computer graphics) Engines Interpolation Multimedia computing Signal processing Hardware Computer displays Concurrent computing
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in