NDLI: A sine/cosine direct digital frequency synthesizer using an angle rotation algorithm

Content Provider	IEEE Xplore Digital Library
Author	Madisetti, A. Kwentus, A. Willson Jr., A.N.
Copyright Year	1995
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Madisetti, A.; Kwentus, A.; Willson, A.N., Jr.)
Abstract	A quadrature direct digital frequency synthesizer (DDFS) produces 16 b sine and cosine outputs with a spurious-free dynamic range greater than 100 dBc and a tuning resolution of 0.0015 Hz at a sample rate of 100 MHz. The prototype IC contains 58,000 transistors in a core area of12 mm/sup 2/ in 1.0 /spl mu/m CMOS and dissipates 1.4 W at 100 MHz. Instead of table lookup, an angle-rotation algorithm implemented as a multiplierless feedforward datapath is used that allows easy pipelining and limits the accumulation of roundoff errors. The modular architecture permits outputs of arbitrary precision by cascading enough angle rotation stages in the datapath. The IC has a 36 b frequency control word giving a tuning resolution of 0.0015 Hz at 100 MHz. To achieve the 100 MHz clock rate in 1.0 /spl mu/m CMOS, the phase accumulator is partitioned into 22 b and 14 b carry-select adder sections. The accumulator output is truncated to 22 b providing greater than 100 dB SFDR.
Starting Page	262
Ending Page	263
File Size	274360
Page Count	2
File Format	PDF
ISBN	0780324951
ISSN	01936530
DOI	10.1109/ISSCC.1995.535548
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Tuning Dynamic range Prototypes CMOS integrated circuits Table lookup Pipeline processing Roundoff errors Frequency control Clocks
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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