NDLI: An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors

Content Provider	IEEE Xplore Digital Library
Author	Tretz, C. Chen Guo Jacobowitz, L.
Copyright Year	2010
Description	Author affiliation: IBM San Jose Design Center, Almaden Research Center, 650 Harry Road, CA 95120, USA (Tretz, C.; Chen Guo; Jacobowitz, L.)
Abstract	Low power design has always been critical to high performance. With the latest technologies, being able to significantly reduce any portion of the overall system power becomes an absolute requirement for extending the lifetime of the system. Clock generation and clock tree distribution are always identified as a significant portion of the power dissipated in a chip. We describe here a servocontrol circuit method that will provide both a lower power clock generation scheme as well as automated power management using the clock elements. The self correcting nature of the circuits proposed also offer good immunity against hysteresis effects.
Starting Page	1
Ending Page	2
File Size	546359
Page Count	2
File Format	PDF
ISBN	9781424491308
ISSN	1078621X
e-ISBN	9781424491292
e-ISBN	9781424491285
DOI	10.1109/SOI.2010.5641401
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Hysteresis Multicore processing Automatic frequency control Table lookup Jacobian matrices Monitoring
Content Type	Text
Resource Type	Article

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An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors