NDLI: Wide-Band Simulation and Characterization of Digital Substrate Noise in SOI Technology

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2010 IEEE International SOI Conference (SOI)

2009 IEEE International SOI Conference

2008 IEEE International SOI Conference

2007 IEEE International SOI Conference

2007 IEEE International SOI Conference

Table of contents

Introduction and History

Conference committee

Table of contents

45 nm SOI and Beyond - Getting to a General Purpose Technology

SOI based technology for Smart Power applications

Analog and RF SOI Circuits for Low Power and Harsh Environment Applications

High Performance NMOS Transistors for 45nm SOI Technologies

An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

High hole mobility GeOI pMOSFETs with high-k / metal gate on Ge condensation wafers

Characteristic Study of SOI eSiGe Techonology

Silicon Superlattice on SOI for High Mobility and Reduced Leakage

Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors

Multi-Gate SOI MOSFET Operations in Harsh Environments

Treshold voltage modulation in FinFET devices through Arsenic Ion Implantation into TiN/HfSiON gate stack

Insights into Gate-Underlap Design in FinFETs for Ultra-Low Voltage Analog Performance

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET

Analysis of the FinFET parasitics for improved RF performances

Evaluation of FinFET RF Building Blocks

Analog Operation of Uniaxially Strained FD SOI nMOSFETs in Cryogenic Temperatures

Accurate Modeling and Analysis of Currents in Trapezoidal FinFET Devices

Evaluation and Optimization of FinFET Quantization Error in Porting a Design from Planar Silicon Technology

Study of Fin Profiles and MuGFETs built on SOI Wafers with a Nitride-Oxide Buried Layer (NOx-BL) as the Buried Insulator Layer

Measurement of Thermal Time Constant in 65-nm PD-SOI Technology with Sub-ns Resolution

Modeling and Implementation of Subthreshold Characteristics of Accumulation-Mode MOSFETs for Various SOI Layer Thickness and Impurity Concentrations

Technology-Based Figure of Merit (FOM) for High Voltage LDMOSFETs - Proof of Value of SOI in Power ICs

Geometric Magnetoresistance and Mobility Behavior in Single-Gate and Double-Gate SOI Devices

RF Power NLDMOS Technology Transfer Strategy from the 130nm to the 65nm node on thin SOI

Gate-Controlled Bipolar Action in Ultrathin-Body Dynamic-Threshold SOI MOSFET

Low-Temperature Behavior Simulations of Phonon-Limited Electron Mobility for Sub-10-nm-Thick SOI MOSFET with (111) or (001) Si Surface Channel

Design Optimization of a 35nm Independently-Double-Gated Flexfet SOI Transistor

Effects of High Temperature Anneals and $^{60}Co$ Gamma Ray Irradiation on Strained Silicon-on-Insulator (sSOI)

Circuit Performance Optimization in Advanced PD-SOI CMOS Development

Dual Silicide SOI CMOS Integration with Low-Resistance PtSi PMOS Contacts

A Plasma Damage Mitigation Concept for SOI Technologies: Lightning Rods

65nm CMOS BULK to SOI comparison

NBTI and Concurrent HCI-NBTI Degradation of 65 nm SOI PMOSFETs

High performance, highly reliable FD/SOI I/O MOSFETs in contemporary high-performance PD/SOI CMOS

Scaling Three-Dimensional SOI Integrated-Circuit Technology

Thermal Modeling and Device Noise Properties of 3D-SOI Technology

Thermal Effects of Three Dimensional Integrated Circuit Stacks

3D stacked channels: how series resistances can limit 3D devices performance

Stacked Nanowires ΦFET with Independent Gates: A Novel Device for Ultra-dense Low-Power Applications

Deep-Trench Process Technology for Three-Dimensionally Integrated SOI-Based Image Sensors

Innovative Approach to drive Floating Body Z-RAM® Embedded Memory to 32 nm and beyond

Analysis of Sensing margin in Silicon-On-ONO (SOONO) Device for the Capacitor-less RAM Applications

A Novel Two-Transistor Floating-Body Memory Cell

Optimizing Floating Body Effect & AC performance in 65nm PD-SOI CMOS

SOI Devices and Ring Oscillators on Thin Dielectric Membranes For Pressure Sensing Applications

A SOI CMOS Smart High-Temperature Sensor

Novel Silicon-on-SiC Substrate with Superior Thermal and RF Performance

On the design of 60 GHz integrated antennas on 0.13 μm SOI technology

Integrated Inductors in HR SOI CMOS technologies: on the economic advantage of SOI technologies for the integration of RF applications

High Temperature Antenna Switches in 130 nm SOI Technology

Millimeter wave design with 65 nm LP SOI HR CMOS technology

Linear cellular antenna switch for highly-integrated SOI front-end

Physical IP for SOI design infrastructure

Experimental Hardware Calibrated Compact Models for 50nm n-channel FinFETs

Wide-Band Simulation and Characterization of Digital Substrate Noise in SOI Technology

Discrete Dopant Induced Characteristic Fluctuations in 16nm Multiple-Gate SOI Devices

A Quantum Definition of Threshold Voltage in MuGFETs

Metal Gate Technology using a Dy Dielectric Cap Approach for multiple-V in NMOS FinFETs

A Ta/Mo Interdiffusion Gate Technology for Dual Metal Gate-First FinFET Fabrication

Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultra-Thin Body nMOSFETs with SOI Thickness of Less Than 2 nm

Flexfet: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope

Operation of a Work Function Type SOI Temperature Sensor up to 250°C

A Very Sensitive Pressure Sensor on a SOI-on-Cavity Substrate

2006 IEEE international SOI Conferencee Proceedings

2005 IEEE International SOI Conference Proceedings

2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)

2003 IEEE International Conference on SOI

2002 IEEE International SOI Conference

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199)

1997 IEEE International SOI Conference Proceedings

1996 IEEE International SOI Conference Proceedings

1995 IEEE International SOI Conference Proceedings

Proceedings. IEEE International SOI Conference

Proceedings of 1993 IEEE International SOI Conference

1992 IEEE International SOI Conference

1991 IEEE International SOI Conference Proceedings

Wide-Band Simulation and Characterization of Digital Substrate Noise in SOI Technology

Content Provider	IEEE Xplore Digital Library
Author	Bol, D. Ambroise, R. Roda Neve, C. Raskin, J.-P. Flandre, D.
Copyright Year	2007
Description	Author affiliation: Univ. Catholique de Louvain, Louvain-La-Neuve, Belgium (Bol, D.; Ambroise, R.; Roda Neve, C.; Flandre, D.)
Abstract	The rising integration level of mixed-signal integrated circuits raises new issues for designers. Substrate noise generated by the switching digital part has a detrimental impact on the performance of the analog/RF parts. This contribution introduces simulation and experimental characterization of so-called "digital substrate noise" on a 0.13-μm SOI CMOS process with high resistivity (HR) substrate. To the authors knowledge, it is the first time that that it is addressed in SOI technology at circuit level.
Starting Page	133
Ending Page	134
File Size	461254
Page Count	2
File Format	PDF
ISBN	9781424408795
ISSN	1078621X
DOI	10.1109/SOI.2007.4357888
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wideband Integrated circuit noise Circuit simulation Integrated circuit technology Mixed analog digital integrated circuits Noise generators Radio frequency CMOS process Conductivity CMOS technology
Content Type	Text
Resource Type	Article

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