NDLI: Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 /spl mu/m

Content Provider	IEEE Xplore Digital Library
Author	Burns, J.A. Keast, C.L. Knecht, J.M. Kunz, R.R. Palmateer, S.C. Cann, S. Soares, A. Shaver, D.C.
Copyright Year	1996
Description	Author affiliation: Lincoln Lab., MIT, Lexington, MA, USA (Burns, J.A.)
Abstract	Lincoln Laboratory has developed a fully-depleted silicon-on-insulator (SOI) technology to build integrated circuits designed for very low power operation and fabricated at the limits of optical lithography. A 0.25 /spl mu/m (drawn gate length) fully-depleted SOI CMOS process technology was established using 248-nm optical lithography for initial process demonstrations, and to identify nonlithographic process integration pinch points and SOI material related issues. Design rules and SPICE parameters have been issued for the 0.25 /spl mu/m technology and a multi-project chip set assembled. The process technology has been adapted to Lincoln's 193-nm step-and-scan tool to fabricate O.2 /spl mu/m circuits and provide the first application of 193-nm lithography to a complete CMOS process. This paper describes the performance characteristics of the technology and the enhancements necessary to extend it to 0.15 /spl mu/m.
Starting Page	102
Ending Page	103
File Size	164937
Page Count	2
File Format	PDF
ISBN	0780333152
ISSN	1078621X
DOI	10.1109/SOI.1996.552514
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-09-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Silicon on insulator technology Lithography Integrated circuit technology Integrated optics CMOS process Laboratories Photonic integrated circuits Optical design Optical materials
Content Type	Text
Resource Type	Article

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