NDLI: SOI CMOS front-end technology: options and tradeoffs

Content Provider	IEEE Xplore Digital Library
Author	Antoniadis, D.A.
Copyright Year	1995
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA (Antoniadis, D.A.)
Abstract	There is general agreement that SOI CMOS has the potential of becoming a mainstream technology for future high performance and low-power logic applications. For this to be fulfilled, SOI CMOS technology should be able to support the design and manufacturing of complex future microprocessors. Then, from the design standpoint, SOI CMOS should be nearly identical to bulk CMOS, so that design tools, methodologies, and functional blocks can all be transferred with minimal perturbation. From the manufacturing standpoint, SOI CMOS should produce acceptable yields in circuits with 10 to 100 M transistors which will require process robustness latitude, scalability, and cost equivalent to or better than bulk. From the circuit design standpoint it is generally acknowledged that fully-depleted (FD) MOSFET's will provide the easier transfer path, because of their lack of significant floating-body (FB) effects under normal operation. However, scaled FD-MOSFET's require very thin SOI films which pose several technological challenges. On the other hand, partially-depleted (PD) MOSFET's are easier to make; indeed, their front-end technology can be imported from bulk with minimal perturbation. However, they display prominent FB effects which can pose problems in circuit design. The choice between the FD versus PD option is then recognized as the main SOI front-end technology tradeoff.
Starting Page	1
Ending Page	3
File Size	278550
Page Count	3
File Format	PDF
ISBN	0780325478
DOI	10.1109/SOI.1995.526431
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Circuit synthesis CMOS logic circuits Microprocessors Design methodology Manufacturing processes CMOS process MOSFETs Robustness Scalability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in