NDLI: Identifying performance deviations in thread pools

Content Provider	IEEE Xplore Digital Library
Author	Syer, M.D. Adams, B. Hassan, A.E.
Copyright Year	2011
Description	Author affiliation: Software Analysis and Intelligence Lab (SAIL), School of Computing, Queen's University, Canada (Syer, M.D.; Adams, B.; Hassan, A.E.)
Abstract	Large-scale software systems handle increasingly larger workloads by implementing highly concurrent and distributed design patterns. The thread pool pattern uses pools of pre-existing and reusable threads to limit thread lifecycle over-head (thread creation and destruction) and resource thrashing (thread proliferation). However, these advantages are weighed against performance issues caused by concurrency risks, like synchronization errors or deadlock, and thread pool-specific risks, like poorly tuned pool size or thread leakage. Detecting these performance issues during load testing requires a thorough understanding of how thread pools behave, yet most performance analysts have limited knowledge of the system and are flooded with terabytes of data from load tests. We propose a methodology to identify threads with performance deviations in thread pools. Our methodology ranks threads based on the dissimilarity of their resource usage metrics. A case study on a large-scale industrial software system shows that our methodology can identify threads with performance deviations with an average precision of 100% and an average recall of 76.61%. Our methodology performs very well when ranking long-lived deviations, such as memory leaks, but more work is needed to rank short-lived deviations, such as CPU spikes.
Starting Page	83
Ending Page	92
File Size	1593252
Page Count	10
File Format	PDF
ISBN	9781457706639
ISSN	10636773
e-ISBN	9781457706646
e-ISBN	9781457706622
DOI	10.1109/ICSM.2011.6080775
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Instruction sets Covariance matrix Queueing analysis Synchronization Educational institutions understanding ULS systems thread-pools behaviour-based clustering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Industrial Case Study on Supporting the Comprehension of System Behaviour under Load

Identifying performance deviations in thread pools (2011)

Automatic realization of serial communication

The impact of data normalisation on unsupervised continuous classification of landforms

Instruction-based high-efficient synchronization in a many-core Network-on-Chip processor

Synchronization-Aware Dynamic Thread Scheduling for Improving Performance and Saving Energy in Multi-core Embedded Systems

Prophet Synchronization Thread Model and Compiler Support

Feature Reduction Based on Analysis of Covariance Matrix

Detecting deadlock in programs with data-centric synchronization

Identifying performance deviations in thread pools

Similar Documents

Industrial Case Study on Supporting the Comprehension of System Behaviour under Load

Identifying performance deviations in thread pools (2011)

Automatic realization of serial communication

The impact of data normalisation on unsupervised continuous classification of landforms

Instruction-based high-efficient synchronization in a many-core Network-on-Chip processor

Synchronization-Aware Dynamic Thread Scheduling for Improving Performance and Saving Energy in Multi-core Embedded Systems

Prophet Synchronization Thread Model and Compiler Support

Feature Reduction Based on Analysis of Covariance Matrix

Detecting deadlock in programs with data-centric synchronization

Identifying performance deviations in thread pools