NDLI: ReCBuLC: Reproducing Concurrency Bugs Using Local Clocks

Content Provider	IEEE Xplore Digital Library
Author	Xiang Yuan Chenggang Wu Zhenjiang Wang Jianjun Li Pen-Chung Yew Huang, J. Xiaobing Feng Yanyan Lan Yunji Chen Yong Guan
Copyright Year	2015
Description	Author affiliation: State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China (Xiang Yuan; Chenggang Wu; Zhenjiang Wang; Jianjun Li; Xiaobing Feng; Yunji Chen) \|\| Coll. of Inf. Eng., Capital Normal Univ., Beijing, China (Yong Guan) \|\| Dept. of Comput. Sci. & Eng., Univ. of Minnesota at Twin-Cities, Minneapolis, MN, USA (Pen-Chung Yew) \|\| Key Lab. of Network Data Sci. & Technol., Inst. of Comput. Technol., Beijing, China (Yanyan Lan) \|\| Dept. of Comput. Sci. & Eng., Texas A&M Univ., College Station, TX, USA (Huang, J.)
Abstract	Multi-threaded programs play an increasingly important role in current multi-core environments. Exposing concurrency bugs and debugging such multi-threaded programs have become quite challenging due to their inherent non-determinism. In order to eliminate such non-determinism, many approaches such as record-and-replay and other similar bug reproducing systems have been proposed. However, those approaches often suffer significant performance degradation because they require a large amount of recorded information and/or long analysis and replay time. In this paper, we propose an effective approach, ReCBuLC, to take advantage of the hardware clocks available on modern processors. The key idea is to reduce the recording overhead and analyzing events' global order by using time stamps recorded in each thread. Those timestamps are used to determine the global orders of shared accesses. To avoid the large overhead incurred in accessing system-wide global clock, we opt to use local per-core clocks that incur much less access overhead. We then propose techniques to resolve differences among local clocks and obtain an accurate global event order. By using per-core clocks, state-of-the-art bug reproducing systems such as PRES and CLAP can reduce the recording overheads by 1% ~ 85%, and the analysis time by 84.66% ~ 99.99%, respectively.
Starting Page	824
Ending Page	834
File Size	2373664
Page Count	11
File Format	PDF
ISBN	9781479919345
DOI	10.1109/ICSE.2015.94
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-16
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Program processors Computer bugs Hardware Coherence Concurrent computing Debugging local clock concurrency bug reproducing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in