NDLI: Formal Modelling and Verification of an Asynchronous DLX Pipeline

Content Provider	IEEE Xplore Digital Library
Author	Kapoor, H.K.
Copyright Year	2006
Description	Author affiliation: Dhirubhai Ambani Inst. of Inf. & Commun. Technol., Gandhinagar (Kapoor, H.K.)
Abstract	A five stage pipeline of an asynchronous DLX processor is modelled and its control flow is verified. The model is built using an asynchronous pipeline of latches separated by processing logic. We model two versions of this pipeline: one using latch controllers with four-phase semi-decoupled and another using fully-decoupled protocol. All the processing units are modelled as processes in the PROMELA language of the Spin tool. The model is verified in Spin by means of assertions, LTL properties and progress labels. A useful observation obtained from the study is that: although the semi-decoupled protocol has the potential to hold a data item in every latch, in the presence of processing logic, at most alternate stages can execute at a given time. Its implication being, in the case of control and data hazards no pipeline stalls are necessary, in the case of fully decoupled version, all stages could execute valid instructions at the same time. All the models were verified to be free from deadlock
Sponsorship	IEEE Comput. Soc
Starting Page	118
Ending Page	127
File Size	148210
Page Count	10
File Format	PDF
ISBN	0769526780
DOI	10.1109/SEFM.2006.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Latches Hazards Protocols Clocks Logic Communication system control CMOS technology Process control DH-HEMTs
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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