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Content Provider | IEEE Xplore Digital Library |
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Author | Sathawornwichit, C. Katayama, T. |
Copyright Year | 2005 |
Description | Author affiliation: Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan (Sathawornwichit, C.; Katayama, T.) |
Abstract | Timing characteristic is a crucial point of concern in the design of real-time systems, because the systems are to operates under time-critical conditions. In this paper, we present a verification-driven approach for improving the correctness in the design of real-time systems. Our approach abstracts the details of timing information of the system by using time parameters. We propose parametric timed structure, an extension of timed transition systems, as a model for describing real-time systems. We define the parametric temporal logic PARCTL for specifying timing properties with time parameters. The model checking algorithms for parametric timed system are then proposed. The algorithms derive the necessary and sufficient condition over time parameters. We illustrate the application of our approach by deriving parameter conditions for a mutual exclusion protocol and show that the result of this approach can be used as guidelines for improving the timing correctness in the design of real-time systems. |
File Size | 282425 |
File Format | |
ISBN | 0769524656 |
ISSN | 15301362 |
DOI | 10.1109/APSEC.2005.12 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2005-12-15 |
Publisher Place | Taiwan |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Parametric statistics Real time systems Timing Logic Power system modeling Automata Application software Computer aided manufacturing Mathematical model Information science |
Content Type | Text |
Resource Type | Article |
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