NDLI: A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems

Content Provider	IEEE Xplore Digital Library
Author	Davila, Henry Lopez Liu, Chun-Yi Liu, Wei-Chang Huang, Shen-Jui Jou, Shyh-Jye Chen, Sau-Gee
Copyright Year	2015
Description	Author affiliation: Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan R.O.C. (Davila, Henry Lopez; Liu, Chun-Yi; Liu, Wei-Chang; Huang, Shen-Jui; Jou, Shyh-Jye; Chen, Sau-Gee)
Abstract	This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-23 architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm2.
Starting Page	44
Ending Page	48
File Size	766345
Page Count	5
File Format	PDF
ISSN	21641706
e-ISBN	9781467390941
DOI	10.1109/SOCC.2015.7406907
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-08
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput IEEE 802.15 Standard Computer architecture Baseband OFDM Receivers
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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