NDLI: A current bleeding mixer based on Gilbert-cell featuring LO amplification

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2009 IEEE International SOC Conference (SOCC)

Front cover page

2009 Technical program committee

List of reviewers

Table of contents

Session quick index

Keynote / plenary session

Keynote speaker

Plenary presentation A

Plenary presentation B

Session WA1 FPGA design methodologies

A high-level compilation toolchain for heterogeneous systems

A multi-level simulation approach in a Simulink-based design tool for FPGAs

Efficient runtime performance monitoring of FPGA-based applications

SoC framework for FPGA: A case study of LTE PUSCH receiver

Session WA2 PLL and clocks

Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS

A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator

A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines

Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator

Dual-band CDR using a half-rate linear phase detector

Session WA3 reconfigurable architectures

A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000

Tuning instruction customisation for reconfigurable system-on-chip

Method for improving performance in online routing of reconfigurable nano architectures

Session WB1 A/D converters

Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder

Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique

A high resolution capacitance deviation-to-digital converter utilizing time stretching

Session WB2 embedded systems, multi core, and embedded memory

Adaptive energy-aware latency-constrained DVFS policy for MPSoC

A configurable length, Fused Multiply-Add floating point unit for a VLIW processor

Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter

Asymmetrical Write-assist for single-ended SRAM operation

Session WB3 low-power circuits and architectures

Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs

Design of a complementary folded-cascode operational amplifier

A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm

High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture

Session TA1 circuits for RF and wireless

54–65 GHz six port demodulator

Ultra wideband 32–67GHz phase shift keyed modulator

A linearized low-voltage oscillator-mixer

A current bleeding mixer based on Gilbert-cell featuring LO amplification

Session TA2 NoC power and data flow optimization

When does Network-on-Chip bypassing make sense?

Power optimal Network-on-Chip interconnect design

A flow regulator for On-Chip Communication

High throughput architecture for CLICHÉ Network on Chip

Session TA3 design for testability and verification

A low-cost SOC debug platform based on on-chip test architectures

Comparator testing in a flash A/D converter

A prototype platform for system-on-chip ADC test and measurement

A fully digital power supply noise thermometer

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS

A novel low power, variable resolution pipelined ADC

Correlating op-amp circuit noise with device flicker (1/f) noise for analog design applications

Experimental analysis of substrate isolation techniques for RF-SOC integration

High-purity 56–66GHz quadrupler for V-band radio homodyne and heterodyne transceiver applications

An instruction set architecture independent design method for embedded OFDM-based software defined transmitter

JavaFlow — A Java dataflow machine

Performance analysis of compressed instruction sets on workloads targeted at mobile internet devices

Improved write margin 6T-SRAM for low supply voltage applications

Low-power multiplier design with row and column bypassing

FPGA-based verification methodology of SoC-type CMOS image signal processor

A speech recognition SoC based on ARM7-TDMI core and a MSAC co-processor

Support vector machine FPGA implementation for video shot boundary detection application

Adaptive admission control on the SpiNNaker MPSoC

Comparative reliability analysis between AMBA and network-on-chip: An MPEG-2 case study

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT

Non-overlapping transition encoding for global on-chip interconnect

Smart-flooding: A novel scheme for fault-tolerant NoCs

Modelling control systems in SystemC AMS — Benefits and limitations

Scalable and low power LDPC decoder design using high level algorithmic synthesis

A versatile fading simulator for on-chip verification of MIMO communication systems

Low power RS codec using cell-based reconfigurable processor

Neuro inspired reconfigurable architecture for hardware/software co-design

Capacitance change estimation for an immunosensor chip

RF-MEMS resonator design for parameter characterization

Session TB1 analog circuit techniques

A holistic design approach for systems on chip

Clocked semi-floating-gate ultra low-voltage inverting current mirror

Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technology

Clocked semi-floating-gate ultra low-voltage symmetric and bidirectional current mirror

Session TB2 system level design for manufacturing

Generic integer linear programming formulation for 3D IC partitioning

SPICE versus STA tools: Challenges and tips for better correlation

OAL: An obstacle-aware legalization in standard cell placement with displacement minimization

Automatic debugging of System-on-a-Chip designs

Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy

Session TB3 data processing architectures

A reconfigurable co-processor for GMM-based classifier

NFA decomposition and multiprocessing architecture for parallel regular expression processing

DDR3 based lookup circuit for high-performance network processing

Session FA1 low-power design methodologies and IP cores

Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT

Fast dynamic power estimation considering glitch filtering

Variation aware low power buffered interconnect design

A low-power pairing-based cryptographic accelerator for embedded security applications

Session FA2 NoC design tools and digital signal processing

An adaptive congestion-aware routing algorithm for mesh network-on-chip platform

A floorplan-aware interactive tool flow for NoC design and synthesis

A Radix $2^{2}$ based parallel pipeline FFT processor for MB-OFDM UWB system

ASIC evaluation of ECHO hash function

Session FB1 system level architecture exploration

A DSL for the SegBus platform

Accurate power estimation of hardware co-processors using system level simulation

Generating interacting synchronous and asynchronous designs from simulink descriptions

Tuning SoCs using the global dynamic critical path

High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath

Session FB2 imaging and video processing

High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODEC

FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding

Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams

Pixel-Parallel SPIHT for frame memory compression

System-on-System (SoS) architecture for 3-D secure imaging

Embedded tutorials

Designing multi-processor Systems-on-Chip

Microwave IC design for broadband receivers

Design in the nano-scale Era: Low-power, reliability, and error resiliency

Introduction to the SystemC AMS DRAFT standard

2008 IEEE International SOC Conference

2007 IEEE International SOC Conference

2006 IEEE International SOC Conference

Proceedings 2005 IEEE International SOC Conference

IEEE International SOC Conference, 2004. Proceedings.

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings.

A current bleeding mixer based on Gilbert-cell featuring LO amplification

Content Provider	IEEE Xplore Digital Library
Author	Kai Xuan Kim Fung Tsang Shu Chuen Lee Wah Ching Lee
Copyright Year	2009
Description	Author affiliation: Department of Electronic Engineering, City University of Hong Kong (Kai Xuan; Kim Fung Tsang; Shu Chuen Lee; Wah Ching Lee)
Abstract	A high gain and low noise mixer based on current bleeding topology is implemented. The high performance is attributed to the effect of current injection and local oscillator (LO) amplification. The conversion gain of the mixer is 17.5 dB at −14 dBm LO power and the noise figure is 10.5 dB. The proposed topology dramatically relieves the typically high power requirement of LO. The mixer is implemented by a 0.18-μm CMOS process. The operating frequency is 2.4 GHz with 10 MHz intermediate frequency. The circuit drains 12 mA current from a 1.5 V supply voltage.
Starting Page	137
Ending Page	140
File Size	920077
Page Count	4
File Format	PDF
ISBN	9781424449408
DOI	10.1109/SOCCON.2009.5398076
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-09
Publisher Place	Ireland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hemorrhaging
Content Type	Text
Resource Type	Article

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