Loading...
Please wait, while we are loading the content...
Precise thickness control for ultra-thin SOI in ELTRAN/spl reg/ SOI-Epi/spl trade/ wafer
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sato, N. Kakizaki, Y. Atoji, T. Notsu, K. Miyabayashi, H. Ito, M. Yonehara, T. |
| Copyright Year | 2002 |
| Description | Author affiliation: ELTRAN Bus. Center, Canon Inc., Kanagawa, Japan (Sato, N.; Kakizaki, Y.; Atoji, T.; Notsu, K.; Miyabayashi, H.; Ito, M.; Yonehara, T.) In ultra-thin-SOI MOSFET, especially in fully depleted operation, threshold voltage is strongly affected by SOI thickness in addition to dopant concentration. For instance, 5 % of tolerance is proposed in ITRS2001. This paper discusses the SOI thickness uniformity in various periods of undulations, especially focusing on ELTRAN SOI-Epi wafers, that is formed by bonding of epitaxial layer on porous Si, splitting, etching back of porous Si, and final Hz annealing to smooth the SOI surface. |
| Sponsorship | IEEE Electron Devices Soc |
| Starting Page | 209 |
| Ending Page | 210 |
| File Size | 167760 |
| Page Count | 2 |
| File Format | |
| ISBN | 0780374398 |
| DOI | 10.1109/SOI.2002.1044479 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-10-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon on insulator technology MOSFETs Thickness control Semiconductor epitaxial layers Annealing |
| Content Type | Text |
| Resource Type | Article |
