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Fringing-induced barrier lowering (FIBL) effects of 100 nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lin, S.C. Kuo, J.B. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada (Lin, S.C.; Kuo, J.B.) This paper reports the fringing-induced barrier lowering (FIBL) effects of 100 nm FD SOI NMOS devices with high permittivity gate dielectrics and LDD/sidewall oxide spacer structure. Based on the study, with a higher k gate dielectric, the subthreshold slope is less steep due to the reduced potential barrier in the surface channel caused by a larger vertical electric field in the LDD region under the sidewall oxide spacer next to the drain. |
| Sponsorship | IEEE Electron Devices Soc |
| Starting Page | 93 |
| Ending Page | 94 |
| File Size | 103509 |
| Page Count | 2 |
| File Format | |
| ISBN | 0780374398 |
| DOI | 10.1109/SOI.2002.1044431 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-10-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon on insulator technology MOS integrated circuits MIS devices |
| Content Type | Text |
| Resource Type | Article |
